diff options
| author | Andre Przywara <andre.przywara@arm.com> | 2022-11-17 17:30:43 +0000 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2023-03-22 13:33:22 +0000 |
| commit | b8f03d29e172af7bd576eafbce9d485a9f626e2e (patch) | |
| tree | b40c972d2a8c0a188db3528ccbe73f8e73fbe230 /include/arch | |
| parent | 4f5ef849c184313a2ba124ff0dd0b1545ddee217 (diff) | |
| download | arm-trusted-firmware-b8f03d29e172af7bd576eafbce9d485a9f626e2e.tar.gz | |
refactor(cpufeat): enable FEAT_ECV for FEAT_STATE_CHECKED
At the moment we only support FEAT_ECV to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime detection (ENABLE_FEAT_ECV=2), by splitting
is_feat_ecv_present() into an ID register reading function and a second
function to report the support status. That function considers both
build time settings and runtime information (if needed), and is used
before we access the CNTPOFF_EL2 system register.
Also move the context saving code from assembly to C, and use the new
is_feat_ecv_supported() function to guard its execution.
Change the FVP platform default to the now supported dynamic option (=2),
so the right decision can be made by the code at runtime.
Change-Id: I4acd5384929f1902b62a87ae073aafa1472cd66b
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'include/arch')
| -rw-r--r-- | include/arch/aarch64/arch_features.h | 31 | ||||
| -rw-r--r-- | include/arch/aarch64/arch_helpers.h | 3 |
2 files changed, 31 insertions, 3 deletions
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h index bdfdc4cce..029cdd112 100644 --- a/include/arch/aarch64/arch_features.h +++ b/include/arch/aarch64/arch_features.h @@ -143,10 +143,35 @@ static inline bool is_feat_fgt_supported(void) return read_feat_fgt_id_field() != 0U; } -static inline unsigned long int get_armv8_6_ecv_support(void) +static unsigned int read_feat_ecv_id_field(void) { - return ((read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_ECV_SHIFT) & - ID_AA64MMFR0_EL1_ECV_MASK); + return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_ECV); +} + +static inline bool is_feat_ecv_supported(void) +{ + if (ENABLE_FEAT_ECV == FEAT_STATE_DISABLED) { + return false; + } + + if (ENABLE_FEAT_ECV == FEAT_STATE_ALWAYS) { + return true; + } + + return read_feat_ecv_id_field() != 0U; +} + +static inline bool is_feat_ecv_v2_supported(void) +{ + if (ENABLE_FEAT_ECV == FEAT_STATE_DISABLED) { + return false; + } + + if (ENABLE_FEAT_ECV == FEAT_STATE_ALWAYS) { + return true; + } + + return read_feat_ecv_id_field() >= ID_AA64MMFR0_EL1_ECV_SELF_SYNCH; } static inline bool is_armv8_5_rng_present(void) diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h index 6d115c7e5..720f6f3bd 100644 --- a/include/arch/aarch64/arch_helpers.h +++ b/include/arch/aarch64/arch_helpers.h @@ -590,6 +590,9 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(hfgitr_el2, HFGITR_EL2) DEFINE_RENAME_SYSREG_RW_FUNCS(hfgrtr_el2, HFGRTR_EL2) DEFINE_RENAME_SYSREG_RW_FUNCS(hfgwtr_el2, HFGWTR_EL2) +/* ARMv8.6 FEAT_ECV Register */ +DEFINE_RENAME_SYSREG_RW_FUNCS(cntpoff_el2, CNTPOFF_EL2) + /* FEAT_HCX Register */ DEFINE_RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2) |