diff options
| author | Mark Brown <broonie@kernel.org> | 2023-03-14 20:13:03 +0000 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2023-03-16 16:45:31 +0000 |
| commit | d3331603664ca7d4ab1510df09e722e6ffb1df29 (patch) | |
| tree | 9a61175c48c3511fcf8e4ac10f5d4cc2d180b1af /include/arch | |
| parent | 4c985e867469523f91588a2f76bbb5ee5ca53d05 (diff) | |
| download | arm-trusted-firmware-d3331603664ca7d4ab1510df09e722e6ffb1df29.tar.gz | |
feat(tcr2): support FEAT_TCR2
Arm v8.9 introduces FEAT_TCR2, adding extended translation control
registers. Support this, context switching TCR2_EL2 and disabling
traps so lower ELs can access the new registers.
Change the FVP platform to default to handling this as a dynamic option so
the right decision can be made by the code at runtime.
Signed-off-by: Mark Brown <broonie@kernel.org>
Change-Id: I297452acd8646d58bac64fc15e05b06a543e5148
Diffstat (limited to 'include/arch')
| -rw-r--r-- | include/arch/aarch64/arch.h | 12 | ||||
| -rw-r--r-- | include/arch/aarch64/arch_features.h | 18 | ||||
| -rw-r--r-- | include/arch/aarch64/arch_helpers.h | 6 |
3 files changed, 36 insertions, 0 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 9e4a3b7bb..b78652103 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -349,6 +349,12 @@ #define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1) #define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2) +/* ID_AA64MMFR3_EL1 definitions */ +#define ID_AA64MMFR3_EL1 S3_0_C0_C7_3 + +#define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0) +#define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf) + /* ID_AA64PFR1_EL1 definitions */ #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) @@ -501,6 +507,7 @@ #define SCR_GPF_BIT (UL(1) << 48) #define SCR_TWEDEL_SHIFT U(30) #define SCR_TWEDEL_MASK ULL(0xf) +#define SCR_TCR2EN_BIT (UL(1) << 43) #define SCR_TRNDR_BIT (UL(1) << 40) #define SCR_HXEn_BIT (UL(1) << 38) #define SCR_ENTP2_SHIFT U(41) @@ -1302,6 +1309,11 @@ #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) /******************************************************************************* + * FEAT_TCR2 - Extended Translation Control Register + ******************************************************************************/ +#define TCR2_EL2 S3_4_C2_C0_3 + +/******************************************************************************* * Definitions for DynamicIQ Shared Unit registers ******************************************************************************/ #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h index 9ff81aa10..582aed12f 100644 --- a/include/arch/aarch64/arch_features.h +++ b/include/arch/aarch64/arch_features.h @@ -131,6 +131,24 @@ static inline bool is_armv8_5_rng_present(void) ID_AA64ISAR0_RNDR_MASK); } +static unsigned int read_feat_tcrx_id_field(void) +{ + return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_TCRX); +} + +static inline bool is_feat_tcr2_supported(void) +{ + if (ENABLE_FEAT_TCR2 == FEAT_STATE_DISABLED) { + return false; + } + + if (ENABLE_FEAT_TCR2 == FEAT_STATE_ALWAYS) { + return true; + } + + return read_feat_tcrx_id_field() != 0U; +} + /******************************************************************************* * Functions to identify the presence of the Activity Monitors Extension ******************************************************************************/ diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h index 3350c8f90..81e0e0643 100644 --- a/include/arch/aarch64/arch_helpers.h +++ b/include/arch/aarch64/arch_helpers.h @@ -579,6 +579,12 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(hfgwtr_el2, HFGWTR_EL2) /* FEAT_HCX Register */ DEFINE_RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2) +/* Armv8.9 system registers */ +DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr3_el1, ID_AA64MMFR3_EL1) + +/* FEAT_TCR2 Register */ +DEFINE_RENAME_SYSREG_RW_FUNCS(tcr2_el2, TCR2_EL2) + /* DynamIQ Shared Unit power management */ DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1) |