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| author | Juan Pablo Conde <juanpablo.conde@arm.com> | 2023-02-22 10:09:52 -0600 |
|---|---|---|
| committer | Juan Pablo Conde <juanpablo.conde@arm.com> | 2023-04-12 15:26:41 -0500 |
| commit | ddb615b419074727ac0a1430cf0f88bd018ac8df (patch) | |
| tree | 762202c1a5d195cbc9c617bae427147b7f01e52a /include/arch | |
| parent | a1c924df6d31bfa93710f1c7e84b3ba34f06c5cb (diff) | |
| download | arm-trusted-firmware-ddb615b419074727ac0a1430cf0f88bd018ac8df.tar.gz | |
feat(hcx): initialize HCRX_EL2 to its default value
The value of register HCRX_EL2 is UNKNOWN out of reset. This can
affect the behavior in lower exception levels, such as traps to
EL2 due to a wrong configuration of the register upon reset.
This patch initializes the register at EL3 and disables all traps
related to it.
On the other hand, new fields have been introduced for HCRX_EL2,
which are now defined in this patch, so they can be used in
further development.
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: I0bf1e949aa0d3be9f227358ad088a1ecb96ce222
Diffstat (limited to 'include/arch')
| -rw-r--r-- | include/arch/aarch64/arch.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index dee7fdcff..596d02075 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -1309,11 +1309,19 @@ * FEAT_HCX - Extended Hypervisor Configuration Register ******************************************************************************/ #define HCRX_EL2 S3_4_C1_C2_2 +#define HCRX_EL2_MSCEn_BIT (UL(1) << 11) +#define HCRX_EL2_MCE2_BIT (UL(1) << 10) +#define HCRX_EL2_CMOW_BIT (UL(1) << 9) +#define HCRX_EL2_VFNMI_BIT (UL(1) << 8) +#define HCRX_EL2_VINMI_BIT (UL(1) << 7) +#define HCRX_EL2_TALLINT_BIT (UL(1) << 6) +#define HCRX_EL2_SMPME_BIT (UL(1) << 5) #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) #define HCRX_EL2_FnXS_BIT (UL(1) << 3) #define HCRX_EL2_EnASR_BIT (UL(1) << 2) #define HCRX_EL2_EnALS_BIT (UL(1) << 1) #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) +#define HCRX_EL2_INIT_VAL ULL(0x0) /******************************************************************************* * FEAT_TCR2 - Extended Translation Control Register |