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| author | Rohit Mathew <rohit.mathew@arm.com> | 2022-11-11 18:45:11 +0000 |
|---|---|---|
| committer | Rohit Mathew <rohit.mathew@arm.com> | 2023-01-23 10:57:25 +0000 |
| commit | ed804406bf2ee04bde1c17683cec6f679ea1e160 (patch) | |
| tree | b2b503223474408837d1ab4de0398993458d876a /include/arch | |
| parent | 982f8e1997523cb24e207f205b841d53b466035a (diff) | |
| download | arm-trusted-firmware-ed804406bf2ee04bde1c17683cec6f679ea1e160.tar.gz | |
fix(mpam): run-time checks for mpam save/restore routines
With "ENABLE_MPAM_FOR_LOWER_ELS" and "CTX_INCLUDE_EL2_REGS" build
options enabled, MPAM EL2 registers would be saved/restored as part of
context management. Context save/restore routines as of now would
proceed to access all of MPAM EL2 registers without any runtime checks.
MPAM specification states that MPAMHCR_EL2 should only be accessed if
MPAMIDR_EL1.HAS_HCR is "1". Likewise, MPAMIDR_EL1.VPMR_MAX has to be
probed to obtain the maximum supported MPAMVPM<x>_EL2 before accessing
corresponding MPAMVPM<x>_EL2 registers. Since runtime checks are not
being made, an exception would be raised if the platform under test
doesn't support one of the registers. On Neoverse reference design
platforms, an exception is being raised while MPAMVPM2_EL2 or above are
accessed. Neoverse reference design platforms support only registers
till MPAMVPM1_EL2 at this point.
To resolve this, add sufficient runtime checks in MPAM EL2 context
save/restore routines. As part of the new save/restore routines,
MPAMIDR_EL1.HAS_HCR and MPAMIDR_EL1.VPMR_MAX are probed for the right
set of registers to be saved and restored.
CC: Davidson Kumaresan <davidson.kumaresan@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I2e3affd23091023b287b2bd5057a4a549037b611
Diffstat (limited to 'include/arch')
| -rw-r--r-- | include/arch/aarch64/arch.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 9e13c3d10..9e4a3b7bb 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -1063,13 +1063,17 @@ #define PMBLIMITR_EL1 S3_0_C9_C10_0 /******************************************************************************* - * Definitions for system register interface to MPAM + * Definitions for system register interface, shifts and masks for MPAM ******************************************************************************/ #define MPAMIDR_EL1 S3_0_C10_C4_4 #define MPAM2_EL2 S3_4_C10_C5_0 #define MPAMHCR_EL2 S3_4_C10_C4_0 #define MPAM3_EL3 S3_6_C10_C5_0 +#define MPAMIDR_EL1_HAS_HCR_SHIFT ULL(0x11) +#define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(0x12) +#define MPAMIDR_EL1_VPMR_MAX_WIDTH ULL(0x3) +#define MPAMIDR_EL1_VPMR_MAX_POSSIBLE ULL(0x7) /******************************************************************************* * Definitions for system register interface to AMU for FEAT_AMUv1 ******************************************************************************/ |