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authorAndre Przywara <andre.przywara@arm.com>2023-01-25 12:26:14 +0000
committerAndre Przywara <andre.przywara@arm.com>2023-02-27 18:04:14 +0000
commitfd1dd4cb2c88f64a411c8482007e4669a563b80d (patch)
tree03d08c3c1a61d597e57ba48702ae6c71d093872d /include/arch
parent3d2da6f5d3a931d97e0294f0a565b1810a55ab98 (diff)
downloadarm-trusted-firmware-fd1dd4cb2c88f64a411c8482007e4669a563b80d.tar.gz
refactor(cpufeat): wrap CPU ID register field isolation
Some MISRA test complains about our code to isolate CPU ID register fields: the ID registers (and associated masks) are 64 bits wide, but the eventual field is always 4 bits wide only, so we use an unsigned int to represent that. MISRA dislikes the differing width here. Since the code to extract a feature field from a CPU ID register is very schematic already, provide a wrapper macro to make this more readable, and do the proper casting in one central place on the way. While at it, use the same macro for the AArch32 feature detection side. Change-Id: Ie102a9e7007a386f5879ec65e159ff041504a4ee Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'include/arch')
-rw-r--r--include/arch/aarch32/arch_features.h11
-rw-r--r--include/arch/aarch64/arch_features.h14
2 files changed, 13 insertions, 12 deletions
diff --git a/include/arch/aarch32/arch_features.h b/include/arch/aarch32/arch_features.h
index ddf09680b..a7d3fe605 100644
--- a/include/arch/aarch32/arch_features.h
+++ b/include/arch/aarch32/arch_features.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,16 +11,17 @@
#include <arch_helpers.h>
+#define ISOLATE_FIELD(reg, feat) \
+ ((unsigned int)(((reg) >> (feat ## _SHIFT)) & (feat ## _MASK)))
+
static inline bool is_armv7_gentimer_present(void)
{
- return ((read_id_pfr1() >> ID_PFR1_GENTIMER_SHIFT) &
- ID_PFR1_GENTIMER_MASK) != 0U;
+ return ISOLATE_FIELD(read_id_pfr1(), ID_PFR1_GENTIMER) != 0U;
}
static inline bool is_armv8_2_ttcnp_present(void)
{
- return ((read_id_mmfr4() >> ID_MMFR4_CNP_SHIFT) &
- ID_MMFR4_CNP_MASK) != 0U;
+ return ISOLATE_FIELD(read_id_mmfr4(), ID_MMFR4_CNP) != 0U;
}
#endif /* ARCH_FEATURES_H */
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 2b801ac84..14f5cc775 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,6 +12,9 @@
#include <arch_helpers.h>
#include <common/feat_detect.h>
+#define ISOLATE_FIELD(reg, feat) \
+ ((unsigned int)(((reg) >> (feat ## _SHIFT)) & (feat ## _MASK)))
+
static inline bool is_armv7_gentimer_present(void)
{
/* The Generic Timer is always present in an ARMv8-A implementation */
@@ -100,8 +103,7 @@ static inline bool is_armv8_6_twed_present(void)
static unsigned int read_feat_fgt_id_field(void)
{
- return (read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_FGT_SHIFT) &
- ID_AA64MMFR0_EL1_FGT_MASK;
+ return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_FGT);
}
static inline bool is_feat_fgt_supported(void)
@@ -134,8 +136,7 @@ static inline bool is_armv8_5_rng_present(void)
******************************************************************************/
static unsigned int read_feat_amu_id_field(void)
{
- return (read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT) &
- ID_AA64PFR0_AMU_MASK;
+ return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_AMU);
}
static inline bool is_feat_amu_supported(void)
@@ -175,8 +176,7 @@ static inline unsigned int get_mpam_version(void)
static inline unsigned int read_feat_hcx_id_field(void)
{
- return (read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_HCX_SHIFT) &
- ID_AA64MMFR1_EL1_HCX_MASK;
+ return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_HCX);
}
static inline bool is_feat_hcx_supported(void)