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| author | Sheetal Tigadoli <sheetal.tigadoli@broadcom.com> | 2019-04-12 15:28:44 +0530 |
|---|---|---|
| committer | Manish Pandey <manish.pandey2@arm.com> | 2019-12-23 15:32:24 +0000 |
| commit | ba4b453b595344d4b9c21d85ac07aa2fa4928c96 (patch) | |
| tree | d0d9a2755887ae93aa5d3ab58f8d7a37527759bd /include | |
| parent | 86ed8953b5233570c49a58060d424b7863d3a396 (diff) | |
| download | arm-trusted-firmware-ba4b453b595344d4b9c21d85ac07aa2fa4928c96.tar.gz | |
lib: cpu: Add additional field definition for A72 L2 control
Add additional field definitions for
Cortex_A72 L2 Control registers
Change-Id: I5ef3a6db41cd7c5d9904172720682716276b7889
Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a72.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h index 4a444c67a..28b440e19 100644 --- a/include/lib/cpus/aarch64/cortex_a72.h +++ b/include/lib/cpus/aarch64/cortex_a72.h @@ -43,7 +43,14 @@ ******************************************************************************/ #define CORTEX_A72_L2ACTLR_EL1 S3_1_C15_C0_0 +#define CORTEX_A72_L2ACTLR_FORCE_TAG_BANK_CLK_ACTIVE (ULL(1) << 28) +#define CORTEX_A72_L2ACTLR_FORCE_L2_LOGIC_CLK_ACTIVE (ULL(1) << 27) +#define CORTEX_A72_L2ACTLR_FORCE_L2_GIC_TIMER_RCG_CLK_ACTIVE (ULL(1) << 26) #define CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN (ULL(1) << 14) +#define CORTEX_A72_L2ACTLR_DISABLE_DSB_WITH_NO_DVM_SYNC (ULL(1) << 11) +#define CORTEX_A72_L2ACTLR_DISABLE_DVM_CMO_BROADCAST (ULL(1) << 8) +#define CORTEX_A72_L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT (ULL(1) << 7) +#define CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI (ULL(1) << 6) /******************************************************************************* * L2 Control register specific definitions. @@ -51,8 +58,12 @@ #define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2 #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) +#define CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT U(5) #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) +#define CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT U(9) +#define CORTEX_A72_L2_DATA_RAM_LATENCY_MASK U(0x7) +#define CORTEX_A72_L2_TAG_RAM_LATENCY_MASK U(0x7) #define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) #define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1) #define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) |