diff options
| author | Mark Brown <broonie@kernel.org> | 2023-03-14 21:33:04 +0000 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2023-04-18 12:36:52 +0100 |
| commit | 688ab57b9349adb19277d88f2469ceeadb8ba083 (patch) | |
| tree | 062101095883b1045695d91d53c87c1de8fa2bc7 /lib/el3_runtime | |
| parent | ffc56bd02d66b524193aeebdf4dea7c9dc14ca8d (diff) | |
| download | arm-trusted-firmware-688ab57b9349adb19277d88f2469ceeadb8ba083.tar.gz | |
feat(gcs): support guarded control stack
Arm v9.4 introduces support for Guarded Control Stack, providing
mitigations against some forms of RPO attacks and an efficient mechanism
for obtaining the current call stack without requiring a full stack
unwind. Enable access to this feature for EL2 and below, context
switching the newly added EL2 registers as appropriate.
Change the FVP platform to default to handling this as a dynamic option
so the right decision can be made by the code at runtime.
Signed-off-by: Mark Brown <broonie@kernel.org>
Change-Id: I691aa7c22e3547bb3abe98d96993baf18c5f0e7b
Diffstat (limited to 'lib/el3_runtime')
| -rw-r--r-- | lib/el3_runtime/aarch64/context_mgmt.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index c411b73ab..e38b34dcd 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -376,6 +376,13 @@ static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *e } /* + * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. + */ + if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { + scr_el3 |= SCR_GCSEn_BIT; + } + + /* * CPTR_EL3 was initialized out of reset, copy that value to the * context register. */ @@ -1039,6 +1046,10 @@ void cm_el2_sysregs_context_save(uint32_t security_state) if (is_feat_sxpoe_supported()) { write_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2, read_por_el2()); } + if (is_feat_gcs_supported()) { + write_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2, read_gcspr_el2()); + write_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2, read_gcscr_el2()); + } } } @@ -1116,6 +1127,10 @@ void cm_el2_sysregs_context_restore(uint32_t security_state) if (is_feat_sxpoe_supported()) { write_por_el2(read_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2)); } + if (is_feat_gcs_supported()) { + write_gcscr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2)); + write_gcspr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2)); + } } } #endif /* CTX_INCLUDE_EL2_REGS */ |