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| author | Manish Pandey <manish.pandey2@arm.com> | 2023-02-10 12:57:17 +0100 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2023-02-10 12:57:17 +0100 |
| commit | 904da6f18099c2a10c41a198cb7da6e17fc4758c (patch) | |
| tree | 736b8e691983d6460115a792d4aa42260b4d455e /lib/el3_runtime | |
| parent | a13b4cd78b6888d767967dfcbf2f2ddc23e4aced (diff) | |
| parent | 01cf14dd41cae9c68cb5e76a815747a0d2a19a4a (diff) | |
| download | arm-trusted-firmware-904da6f18099c2a10c41a198cb7da6e17fc4758c.tar.gz | |
Merge "fix(context-mgmt): enable SCXTNUM access" into integration
Diffstat (limited to 'lib/el3_runtime')
| -rw-r--r-- | lib/el3_runtime/aarch64/context_mgmt.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 3bcefdb5d..dab25d681 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -169,7 +169,12 @@ static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_inf state = get_el3state_ctx(ctx); scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); - scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT | SCR_EnSCXT_BIT; + scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; + +#if ENABLE_FEAT_CSV2_2 + /* Enable access to the SCXTNUM_ELx registers. */ + scr_el3 |= SCR_EnSCXT_BIT; +#endif write_ctx_reg(state, CTX_SCR_EL3, scr_el3); } @@ -222,6 +227,11 @@ static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info * scr_el3 |= SCR_TERR_BIT; #endif +#if ENABLE_FEAT_CSV2_2 + /* Enable access to the SCXTNUM_ELx registers. */ + scr_el3 |= SCR_EnSCXT_BIT; +#endif + #ifdef IMAGE_BL31 /* * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as |