diff options
| author | Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> | 2022-09-19 23:32:08 +0100 |
|---|---|---|
| committer | Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> | 2022-09-29 17:22:14 +0100 |
| commit | d64bfef5a184aa6951a7bc641f80b0d629cc46b4 (patch) | |
| tree | 31979fae778642904370c5f82d464a6c85f8d8e8 /lib/el3_runtime | |
| parent | d8d0ea9a7fcd5ace63a8c863176d9535adfc581d (diff) | |
| download | arm-trusted-firmware-d64bfef5a184aa6951a7bc641f80b0d629cc46b4.tar.gz | |
build(changelog): add new scope for Performance Monitor Extensions
This patch adds a news scope for FEAT_PMUV3, alongside
updating the existing comments related to the saving of
PMCR_EL0 register routine for better understanding.
Change-Id: Ib150244ce94cfcbbe5d12fdae56327c3d72bda0b
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Diffstat (limited to 'lib/el3_runtime')
| -rw-r--r-- | lib/el3_runtime/aarch64/context.S | 28 |
1 files changed, 21 insertions, 7 deletions
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index acfef8052..6b88a9086 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -806,9 +806,9 @@ endfunc fpregs_context_restore /* ------------------------------------------------------------------ * The following macro is used to save and restore all the general * purpose and ARMv8.3-PAuth (if enabled) registers. - * It also checks if Secure Cycle Counter is not disabled in MDCR_EL3 - * when ARMv8.5-PMU is implemented, and if called from Non-secure - * state saves PMCR_EL0 and disables Cycle Counter. + * It also checks if the Secure Cycle Counter (PMCCNTR_EL0) + * is disabled in EL3/Secure (ARMv8.5-PMU), wherein PMCCNTR_EL0 + * needs not to be saved/restored during world switch. * * Ideally we would only save and restore the callee saved registers * when a world switch occurs but that type of implementation is more @@ -837,9 +837,17 @@ endfunc fpregs_context_restore str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] /* ---------------------------------------------------------- - * Check if earlier initialization MDCR_EL3.SCCD/MCCD to 1 - * failed, meaning that FEAT_PMUv3p5/7 is not implemented and - * PMCR_EL0 should be saved in non-secure context. + * Check if earlier initialization of MDCR_EL3.SCCD/MCCD to 1 + * has failed. + * + * MDCR_EL3: + * MCCD bit set, Prohibits the Cycle Counter PMCCNTR_EL0 from + * counting at EL3. + * SCCD bit set, Secure Cycle Counter Disable. Prohibits PMCCNTR_EL0 + * from counting in Secure state. + * If these bits are not set, meaning that FEAT_PMUv3p5/7 is + * not implemented and PMCR_EL0 should be saved in non-secure + * context. * ---------------------------------------------------------- */ mov_imm x10, (MDCR_SCCD_BIT | MDCR_MCCD_BIT) @@ -847,7 +855,13 @@ endfunc fpregs_context_restore tst x9, x10 bne 1f - /* Secure Cycle Counter is not disabled */ + /* ---------------------------------------------------------- + * If control reaches here, it ensures the Secure Cycle + * Counter (PMCCNTR_EL0) is not prohibited from counting at + * EL3 and in secure states. + * Henceforth, PMCR_EL0 to be saved before world switch. + * ---------------------------------------------------------- + */ mrs x9, pmcr_el0 /* Check caller's security state */ |