diff options
| author | Govindraj Raja <govindraj.raja@arm.com> | 2023-03-10 10:38:54 +0000 |
|---|---|---|
| committer | Joanna Farley <joanna.farley@arm.com> | 2023-04-04 17:16:46 +0200 |
| commit | 516a52f6f5cda6acb311ffd6e8fb77f2e09c1357 (patch) | |
| tree | 86d826e37dfea253d47b3a62f50e2518a705a13d /lib | |
| parent | 42fb812a7525682362096d651a3749787b3bd555 (diff) | |
| download | arm-trusted-firmware-516a52f6f5cda6acb311ffd6e8fb77f2e09c1357.tar.gz | |
feat(cpus): add support for chaberton cpu
Add basic CPU library code to support the Chaberton CPU,
Chaberton cores are based out of Hunter core, so overall
library code was adapted based on that.
Change-Id: I58321c77f2c364225a764da6fa65656d1bec33f1
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/cpus/aarch64/cortex_chaberton.S | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/cortex_chaberton.S b/lib/cpus/aarch64/cortex_chaberton.S new file mode 100644 index 000000000..2c47bd381 --- /dev/null +++ b/lib/cpus/aarch64/cortex_chaberton.S @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <common/bl_common.h> +#include <cortex_chaberton.h> +#include <cpu_macros.S> +#include <plat_macros.S> + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex Chaberton must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex Chaberton supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + +func cortex_chaberton_reset_func + /* Disable speculative loads */ + msr SSBS, xzr + isb + ret +endfunc cortex_chaberton_reset_func + + /* ---------------------------------------------------- + * HW will do the cache maintenance while powering down + * ---------------------------------------------------- + */ +func cortex_chaberton_core_pwr_dwn + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + mrs x0, CORTEX_CHABERTON_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_CHABERTON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_CHABERTON_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_chaberton_core_pwr_dwn + +#if REPORT_ERRATA +/* + * Errata printing function for Cortex Chaberton. Must follow AAPCS. + */ +func cortex_chaberton_errata_report + ret +endfunc cortex_chaberton_errata_report +#endif + + /* --------------------------------------------- + * This function provides Cortex Chaberton specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_chaberton_regs, "aS" +cortex_chaberton_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_chaberton_cpu_reg_dump + adr x6, cortex_chaberton_regs + mrs x8, CORTEX_CHABERTON_CPUECTLR_EL1 + ret +endfunc cortex_chaberton_cpu_reg_dump + +declare_cpu_ops cortex_chaberton, CORTEX_CHABERTON_MIDR, \ + cortex_chaberton_reset_func, \ + cortex_chaberton_core_pwr_dwn |