diff options
author | Pranav Madhu <pranav.madhu@arm.com> | 2022-07-27 12:49:24 +0530 |
---|---|---|
committer | Pranav Madhu <pranav.madhu@arm.com> | 2022-09-15 18:09:56 +0530 |
commit | 158ed580bdf5736abfa9f16f61be1ca1609e0e41 (patch) | |
tree | 27e7cffbaa8380ce1303cc1777a05accb1fe21da /plat/arm/css | |
parent | 5cf9cc130a90fd8c4503c57ec4af235b469fd473 (diff) | |
download | arm-trusted-firmware-158ed580bdf5736abfa9f16f61be1ca1609e0e41.tar.gz |
feat(plat/arm/css): add per-cpu power down support for warm reset
Add a new function to setup a SGI interrupt that will be used to trigger
a request for per-cpu power down when executing the PSCI SYSTEM_RESET
request. This will be used on CSS platform that require all the CPUs to
execute the CPU specific power down sequence to complete a warm reboot
sequence in which only the CPUs are power cycled.
Change-Id: I80da0f6c3cd0c5c442c82239ba1e1f773821a7f5
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Diffstat (limited to 'plat/arm/css')
-rw-r--r-- | plat/arm/css/common/css_common.mk | 8 | ||||
-rw-r--r-- | plat/arm/css/common/css_pm.c | 23 |
2 files changed, 29 insertions, 2 deletions
diff --git a/plat/arm/css/common/css_common.mk b/plat/arm/css/common/css_common.mk index 2fbbe4560..c41a1fb26 100644 --- a/plat/arm/css/common/css_common.mk +++ b/plat/arm/css/common/css_common.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -88,3 +88,9 @@ CSS_NON_SECURE_UART := 0 $(eval $(call assert_boolean,CSS_NON_SECURE_UART)) $(eval $(call add_define,CSS_NON_SECURE_UART)) +# Process CSS_SYSTEM_GRACEFUL_RESET flag +# This build option can be used on CSS platforms that require all the CPUs +# to execute the CPU specific power down sequence to complete a warm reboot +# sequence in which only the CPUs are power cycled. +CSS_SYSTEM_GRACEFUL_RESET := 0 +$(eval $(call add_define,CSS_SYSTEM_GRACEFUL_RESET)) diff --git a/plat/arm/css/common/css_pm.c b/plat/arm/css/common/css_pm.c index 926b8ec7c..f4d3b4a59 100644 --- a/plat/arm/css/common/css_pm.c +++ b/plat/arm/css/common/css_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,12 +9,15 @@ #include <platform_def.h> #include <arch_helpers.h> +#include <bl31/interrupt_mgmt.h> #include <common/debug.h> #include <drivers/arm/css/css_scp.h> #include <lib/cassert.h> #include <plat/arm/common/plat_arm.h> #include <plat/arm/css/common/css_pm.h> +#include <plat/common/platform.h> + /* Allow CSS platforms to override `plat_arm_psci_pm_ops` */ #pragma weak plat_arm_psci_pm_ops @@ -110,6 +113,9 @@ void css_pwr_domain_on_finish_late(const psci_power_state_t *target_state) /* Enable the gic cpu interface */ plat_arm_gic_cpuif_enable(); + + /* Setup the CPU power down request interrupt for secondary core(s) */ + css_setup_cpu_pwr_down_intr(); } /******************************************************************************* @@ -331,6 +337,21 @@ static int css_translate_power_state_by_mpidr(u_register_t mpidr, return arm_validate_power_state(power_state, output_state); } +/* + * Setup the SGI interrupt that will be used trigger the execution of power + * down sequence for all the secondary cores. This interrupt is setup to be + * handled in EL3 context at a priority defined by the platform. + */ +void css_setup_cpu_pwr_down_intr(void) +{ +#if CSS_SYSTEM_GRACEFUL_RESET + plat_ic_set_interrupt_type(CSS_CPU_PWR_DOWN_REQ_INTR, INTR_TYPE_EL3); + plat_ic_set_interrupt_priority(CSS_CPU_PWR_DOWN_REQ_INTR, + PLAT_REBOOT_PRI); + plat_ic_enable_interrupt(CSS_CPU_PWR_DOWN_REQ_INTR); +#endif +} + /******************************************************************************* * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard * platform will take care of registering the handlers with PSCI. |