diff options
| author | Jit Loon Lim <jit.loon.lim@intel.com> | 2022-06-15 14:59:33 +0200 |
|---|---|---|
| committer | Sieu Mun Tang <sieu.mun.tang@intel.com> | 2022-11-22 23:35:36 +0800 |
| commit | 3905f57134853f47f6e859b8b6322a7dbbfc49f7 (patch) | |
| tree | 45cbcba4efb3647a38d3a09ddabd1a3dc9543b39 /plat/intel | |
| parent | e6c038909193b83bc293de9b1eb65440e75f8c91 (diff) | |
| download | arm-trusted-firmware-3905f57134853f47f6e859b8b6322a7dbbfc49f7.tar.gz | |
feat(intel): setup FPGA interface for Agilex
Enable/Disable FPGA interfaces based on handoff configuration.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I8667f362aa53e7c68723e0dbd5284844ae39dfb5
Diffstat (limited to 'plat/intel')
| -rw-r--r-- | plat/intel/soc/agilex/include/agilex_pinmux.h | 25 | ||||
| -rw-r--r-- | plat/intel/soc/agilex/soc/agilex_pinmux.c | 24 |
2 files changed, 42 insertions, 7 deletions
diff --git a/plat/intel/soc/agilex/include/agilex_pinmux.h b/plat/intel/soc/agilex/include/agilex_pinmux.h index fe01062c0..07012085a 100644 --- a/plat/intel/soc/agilex/include/agilex_pinmux.h +++ b/plat/intel/soc/agilex/include/agilex_pinmux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +7,25 @@ #ifndef AGX_PINMUX_H #define AGX_PINMUX_H -#define AGX_PINMUX_PIN0SEL 0xffd13000 -#define AGX_PINMUX_IO0CTRL 0xffd13130 -#define AGX_PINMUX_PINMUX_EMAC0_USEFPGA 0xffd13300 -#define AGX_PINMUX_IO0_DELAY 0xffd13400 +#define AGX_PINMUX_BASE 0xffd13000 +#define AGX_PINMUX_PIN0SEL (AGX_PINMUX_BASE + 0x000) +#define AGX_PINMUX_IO0CTRL (AGX_PINMUX_BASE + 0x130) +#define AGX_PINMUX_EMAC0_USEFPGA (AGX_PINMUX_BASE + 0x300) +#define AGX_PINMUX_EMAC1_USEFPGA (AGX_PINMUX_BASE + 0x304) +#define AGX_PINMUX_EMAC2_USEFPGA (AGX_PINMUX_BASE + 0x308) +#define AGX_PINMUX_NAND_USEFPGA (AGX_PINMUX_BASE + 0x320) +#define AGX_PINMUX_SPIM0_USEFPGA (AGX_PINMUX_BASE + 0x328) +#define AGX_PINMUX_SPIM1_USEFPGA (AGX_PINMUX_BASE + 0x32c) +#define AGX_PINMUX_SDMMC_USEFPGA (AGX_PINMUX_BASE + 0x354) +#define AGX_PINMUX_IO0_DELAY (AGX_PINMUX_BASE + 0x400) + +#define AGX_PINMUX_NAND_USEFPGA_VAL BIT(4) +#define AGX_PINMUX_SDMMC_USEFPGA_VAL BIT(8) +#define AGX_PINMUX_SPIM0_USEFPGA_VAL BIT(16) +#define AGX_PINMUX_SPIM1_USEFPGA_VAL BIT(24) +#define AGX_PINMUX_EMAC0_USEFPGA_VAL BIT(0) +#define AGX_PINMUX_EMAC1_USEFPGA_VAL BIT(8) +#define AGX_PINMUX_EMAC2_USEFPGA_VAL BIT(16) #include "socfpga_handoff.h" diff --git a/plat/intel/soc/agilex/soc/agilex_pinmux.c b/plat/intel/soc/agilex/soc/agilex_pinmux.c index 2367c21c7..96e1ade59 100644 --- a/plat/intel/soc/agilex/soc/agilex_pinmux.c +++ b/plat/intel/soc/agilex/soc/agilex_pinmux.c @@ -188,7 +188,27 @@ const uint32_t sysmgr_pinmux_array_iodelay[] = { void config_fpgaintf_mod(void) { - mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_2), 1<<8); + uint32_t val; + + val = 0; + if (mmio_read_32(AGX_PINMUX_NAND_USEFPGA) & 1) + val |= AGX_PINMUX_NAND_USEFPGA_VAL; + if (mmio_read_32(AGX_PINMUX_SDMMC_USEFPGA) & 1) + val |= AGX_PINMUX_SDMMC_USEFPGA_VAL; + if (mmio_read_32(AGX_PINMUX_SPIM0_USEFPGA) & 1) + val |= AGX_PINMUX_SPIM0_USEFPGA_VAL; + if (mmio_read_32(AGX_PINMUX_SPIM1_USEFPGA) & 1) + val |= AGX_PINMUX_SPIM1_USEFPGA_VAL; + mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_2), val); + + val = 0; + if (mmio_read_32(AGX_PINMUX_EMAC0_USEFPGA) & 1) + val |= AGX_PINMUX_EMAC0_USEFPGA_VAL; + if (mmio_read_32(AGX_PINMUX_EMAC1_USEFPGA) & 1) + val |= AGX_PINMUX_EMAC1_USEFPGA_VAL; + if (mmio_read_32(AGX_PINMUX_EMAC2_USEFPGA) & 1) + val |= AGX_PINMUX_EMAC2_USEFPGA_VAL; + mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_3), val); } @@ -209,7 +229,7 @@ void config_pinmux(handoff *hoff_ptr) } for (i = 0; i < 40; i += 2) { - mmio_write_32(AGX_PINMUX_PINMUX_EMAC0_USEFPGA + + mmio_write_32(AGX_PINMUX_EMAC0_USEFPGA + hoff_ptr->pinmux_fpga_array[i], hoff_ptr->pinmux_fpga_array[i+1]); } |