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| author | Arvind Ram Prakash <arvind.ramprakash@arm.com> | 2022-11-22 14:41:00 -0600 |
|---|---|---|
| committer | Maksims Svecovs <maksims.svecovs@arm.com> | 2023-03-15 11:43:14 +0000 |
| commit | 42d4d3baacb3b11c68163ec85de1bf2e34e0c882 (patch) | |
| tree | 5718f07f5a2367f1fb58e3a79d02aa1e1d3587ea /plat/intel | |
| parent | ff65ac24409f0ed5025ff3005ffe4a1f98353166 (diff) | |
| download | arm-trusted-firmware-42d4d3baacb3b11c68163ec85de1bf2e34e0c882.tar.gz | |
refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3
BL2_AT_EL3 is an overloaded macro which has two uses:
1. When BL2 is entry point into TF-A(no BL1)
2. When BL2 is running at EL3 exception level
These two scenarios are not exactly same even though first implicitly
means second to be true. To distinguish between these two use cases we
introduce new macros.
BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2.
Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where
BL2 runs at EL3 (including four world systems).
BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the
repository.
Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
Diffstat (limited to 'plat/intel')
| -rw-r--r-- | plat/intel/soc/agilex/platform.mk | 4 | ||||
| -rw-r--r-- | plat/intel/soc/n5x/platform.mk | 2 | ||||
| -rw-r--r-- | plat/intel/soc/stratix10/platform.mk | 4 |
3 files changed, 5 insertions, 5 deletions
diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index a1e58fcca..e9fa666a5 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. # Copyright (c) 2019-2022, Intel Corporation. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause @@ -77,7 +77,7 @@ BL31_SOURCES += \ plat/intel/soc/common/soc/socfpga_reset_manager.c PROGRAMMABLE_RESET_ADDRESS := 0 -BL2_AT_EL3 := 1 +RESET_TO_BL2 := 1 BL2_INV_DCACHE := 0 MULTI_CONSOLE_API := 1 USE_COHERENT_MEM := 1 diff --git a/plat/intel/soc/n5x/platform.mk b/plat/intel/soc/n5x/platform.mk index be1ad8c6b..4f3da4edb 100644 --- a/plat/intel/soc/n5x/platform.mk +++ b/plat/intel/soc/n5x/platform.mk @@ -46,7 +46,7 @@ BL31_SOURCES += \ plat/intel/soc/common/soc/socfpga_reset_manager.c PROGRAMMABLE_RESET_ADDRESS := 0 -BL2_AT_EL3 := 1 +RESET_TO_BL2 := 1 BL2_INV_DCACHE := 0 MULTI_CONSOLE_API := 1 USE_COHERENT_MEM := 1 diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index b7eb4bd77..6bc96fb6c 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. # Copyright (c) 2019-2022, Intel Corporation. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause @@ -76,5 +76,5 @@ BL31_SOURCES += \ plat/intel/soc/common/soc/socfpga_reset_manager.c PROGRAMMABLE_RESET_ADDRESS := 0 -BL2_AT_EL3 := 1 +RESET_TO_BL2 := 1 USE_COHERENT_MEM := 1 |