diff options
| author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2023-04-11 09:39:11 +0200 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2023-04-11 09:39:11 +0200 |
| commit | f1bdf105d079539cee4d9dbd1c0049159c842efb (patch) | |
| tree | 3acfc15de920ecb8eefb92da936de26fe89aa5f1 /plat/intel | |
| parent | ebb0838a9833ef0923ca094860f6fc6a2869d673 (diff) | |
| parent | 7f7a16a6c0a49af593fa080eb66f72a20bb07299 (diff) | |
| download | arm-trusted-firmware-f1bdf105d079539cee4d9dbd1c0049159c842efb.tar.gz | |
Merge "fix(intel): update boot scratch to indicate to Uboot is PSCI ON" into integration
Diffstat (limited to 'plat/intel')
| -rw-r--r-- | plat/intel/soc/common/socfpga_psci.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/plat/intel/soc/common/socfpga_psci.c b/plat/intel/soc/common/socfpga_psci.c index 5fd6559f2..bdece935c 100644 --- a/plat/intel/soc/common/socfpga_psci.c +++ b/plat/intel/soc/common/socfpga_psci.c @@ -14,6 +14,7 @@ #include "socfpga_mailbox.h" #include "socfpga_plat_def.h" #include "socfpga_reset_manager.h" +#include "socfpga_system_manager.h" #include "socfpga_sip_svc.h" @@ -38,12 +39,19 @@ void socfpga_cpu_standby(plat_local_state_t cpu_state) int socfpga_pwr_domain_on(u_register_t mpidr) { unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr); + uint32_t psci_boot = 0x00; VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr); if (cpu_id == -1) return PSCI_E_INTERN_FAIL; + if (cpu_id == 0x00) { + psci_boot = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)); + psci_boot |= 0x20000; /* bit 17 */ + mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8), psci_boot); + } + mmio_write_64(PLAT_CPUID_RELEASE, cpu_id); /* release core reset */ |