diff options
| author | Andrew Davis <afd@ti.com> | 2023-01-10 13:14:37 -0600 |
|---|---|---|
| committer | Andrew Davis <afd@ti.com> | 2023-01-12 18:42:57 -0600 |
| commit | aee2f33a675891f660fc0d06e739ce85f3472075 (patch) | |
| tree | 45fd80bb3588e3ed6506872215cf50d3f4cd597e /plat/ti | |
| parent | 42c4760afad48714f807c65ddea9d0146a03f0c7 (diff) | |
| download | arm-trusted-firmware-aee2f33a675891f660fc0d06e739ce85f3472075.tar.gz | |
feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles
The Cortex-A72 based cores on K3 platforms can be clocked fast
enough that an extra latency cycle is needed to ensure correct
L2 access. Set the latency here for all A72 cores.
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I639091dd0d2de09572bf0f73ac404e306e336883
Diffstat (limited to 'plat/ti')
| -rw-r--r-- | plat/ti/k3/board/j784s4/board.mk | 4 | ||||
| -rw-r--r-- | plat/ti/k3/common/k3_helpers.S | 10 |
2 files changed, 13 insertions, 1 deletions
diff --git a/plat/ti/k3/board/j784s4/board.mk b/plat/ti/k3/board/j784s4/board.mk index 92433ab65..c7fcb0016 100644 --- a/plat/ti/k3/board/j784s4/board.mk +++ b/plat/ti/k3/board/j784s4/board.mk @@ -17,6 +17,10 @@ $(eval $(call add_define,K3_HW_CONFIG_BASE)) K3_SEC_PROXY_LITE := 0 $(eval $(call add_define,K3_SEC_PROXY_LITE)) +# Use a 4 cycle data RAM latency for J784s4 +K3_DATA_RAM_4_LATENCY := 1 +$(eval $(call add_define,K3_DATA_RAM_4_LATENCY)) + # System coherency is managed in hardware USE_COHERENT_MEM := 1 diff --git a/plat/ti/k3/common/k3_helpers.S b/plat/ti/k3/common/k3_helpers.S index f4f7d18ea..cc9934c4e 100644 --- a/plat/ti/k3/common/k3_helpers.S +++ b/plat/ti/k3/common/k3_helpers.S @@ -105,7 +105,15 @@ func plat_reset_handler /* Cortex-A72 specific settings */ a72: mrs x0, CORTEX_A72_L2CTLR_EL1 - orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) +#if K3_DATA_RAM_4_LATENCY + /* Set L2 cache data RAM latency to 4 cycles */ + orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES << \ + CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) +#else + /* Set L2 cache data RAM latency to 3 cycles */ + orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << \ + CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) +#endif msr CORTEX_A72_L2CTLR_EL1, x0 isb ret |