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| author | Louis Mayencourt <louis.mayencourt@arm.com> | 2020-01-24 13:30:28 +0000 |
|---|---|---|
| committer | Louis Mayencourt <louis.mayencourt@arm.com> | 2020-01-28 11:10:48 +0000 |
| commit | f1be00da0b0acf90355558e01d5f8e1f79c0d481 (patch) | |
| tree | 17f863ee4f3f43cbeaa35e70e72e514774815642 /plat/ti | |
| parent | 262c5d30689403112568979dd6154849037fb122 (diff) | |
| download | arm-trusted-firmware-f1be00da0b0acf90355558e01d5f8e1f79c0d481.tar.gz | |
Use correct type when reading SCR register
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.
Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Diffstat (limited to 'plat/ti')
| -rw-r--r-- | plat/ti/k3/common/k3_psci.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c index de9cefe5b..58588b055 100644 --- a/plat/ti/k3/common/k3_psci.c +++ b/plat/ti/k3/common/k3_psci.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,7 +21,7 @@ uintptr_t k3_sec_entrypoint; static void k3_cpu_standby(plat_local_state_t cpu_state) { - unsigned int scr; + u_register_t scr; scr = read_scr_el3(); /* Enable the Non secure interrupt to wake the CPU */ |