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| author | Tanmay Shah <tanmay.shah@amd.com> | 2022-09-13 11:10:08 -0700 |
|---|---|---|
| committer | Tanmay Shah <tanmay.shah@amd.com> | 2022-09-13 11:19:01 -0700 |
| commit | ac6c135c83fe4efa4d6e9b9c06e899b57ce5647a (patch) | |
| tree | 9d27bc7c674ed4453541136c30168a6131f526f2 /plat/xilinx/zynqmp/pm_service | |
| parent | 207bda950d9cc741a9fa3767219ccc83d8dd2736 (diff) | |
| download | arm-trusted-firmware-ac6c135c83fe4efa4d6e9b9c06e899b57ce5647a.tar.gz | |
fix(zynqmp): ensure memory write finish with dsb()
GICD reg write must complete before core goes to idle
mode. Achieve this with dsb() barrier instruction in IPI
ISR
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: I5af42ca901567ee5e54a5434ebe3e673a92cb9be
Diffstat (limited to 'plat/xilinx/zynqmp/pm_service')
| -rw-r--r-- | plat/xilinx/zynqmp/pm_service/pm_svc_main.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c index f24387a43..82da57c71 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c +++ b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c @@ -151,6 +151,8 @@ static uint64_t __unused __dead2 zynqmp_sgi7_irq(uint32_t id, uint32_t flags, 0xffffffff); } + dsb(); + spin_unlock(&inc_lock); if (active_cores == 0) { |