fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373

58 files changed, 64 insertions, 64 deletions

diff --git a/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c b/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c
index b961da939..705ec384c 100644
--- a/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c
+++ b/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c
@@ -84,7 +84,7 @@ void sp_min_plat_arch_setup(void)
 	     (void *)hw_config_info->config_addr);
 
 	/*
-	 * Preferrably we expect this address and size are page aligned,
+	 * Preferably we expect this address and size are page aligned,
 	 * but if they are not then align it.
 	 */
 	hw_config_base_align = page_align(hw_config_info->config_addr, DOWN);
diff --git a/plat/arm/common/tsp/arm_tsp_setup.c b/plat/arm/common/tsp/arm_tsp_setup.c
index a4da8c35e..df3488bf5 100644
--- a/plat/arm/common/tsp/arm_tsp_setup.c
+++ b/plat/arm/common/tsp/arm_tsp_setup.c
@@ -62,7 +62,7 @@ void tsp_platform_setup(void)
 
 /*******************************************************************************
  * Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the MMU
+ * moment this is only initializes the MMU
  ******************************************************************************/
 void tsp_plat_arch_setup(void)
 {
diff --git a/plat/brcm/board/stingray/driver/swreg.c b/plat/brcm/board/stingray/driver/swreg.c
index 2b7c53b53..a5b5b9f3a 100644
--- a/plat/brcm/board/stingray/driver/swreg.c
+++ b/plat/brcm/board/stingray/driver/swreg.c
@@ -296,7 +296,7 @@ failed:
 	return ret;
 }
 
-/* Update SWREG firmware for all power doman for A2 chip */
+/* Update SWREG firmware for all power domain for A2 chip */
 int swreg_firmware_update(void)
 {
 	enum sw_reg reg_id;
diff --git a/plat/common/aarch64/plat_ehf.c b/plat/common/aarch64/plat_ehf.c
index da768843e..138269033 100644
--- a/plat/common/aarch64/plat_ehf.c
+++ b/plat/common/aarch64/plat_ehf.c
@@ -27,7 +27,7 @@ ehf_pri_desc_t plat_exceptions[] = {
 #if SPM_MM
 	EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SP_PRI),
 #endif
-	/* Plaform specific exceptions description */
+	/* Platform specific exceptions description */
 #ifdef PLAT_EHF_DESC
 	PLAT_EHF_DESC,
 #endif
diff --git a/plat/imx/common/include/sci/sci_rpc.h b/plat/imx/common/include/sci/sci_rpc.h
index 60dbc27b6..b6adf3308 100644
--- a/plat/imx/common/include/sci/sci_rpc.h
+++ b/plat/imx/common/include/sci/sci_rpc.h
@@ -100,7 +100,7 @@ typedef struct sc_rpc_async_msg_s {
 void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, bool no_resp);
 
 /*!
- * This is an internal function to dispath an RPC call that has
+ * This is an internal function to dispatch an RPC call that has
  * arrived via IPC over an MU. It is called by server-side SCFW.
  *
  * @param[in]     mu          MU message arrived on
diff --git a/plat/imx/common/include/sci/svc/pad/sci_pad_api.h b/plat/imx/common/include/sci/svc/pad/sci_pad_api.h
index dc23eedb3..ac93aae3f 100644
--- a/plat/imx/common/include/sci/svc/pad/sci_pad_api.h
+++ b/plat/imx/common/include/sci/svc/pad/sci_pad_api.h
@@ -42,7 +42,7 @@
  *
  * Pads are managed as a resource by the Resource Manager (RM).  They have
  * assigned owners and only the owners can configure the pads. Some of the
- * pads are reserved for use by the SCFW itself and this can be overriden
+ * pads are reserved for use by the SCFW itself and this can be overridden
  * with the implementation of board_config_sc(). Additionally, pads may
  * be assigned to various other partitions via the implementation of
  * board_system_config().
@@ -156,7 +156,7 @@ typedef uint8_t sc_pad_config_t;
  * This type is used to declare a pad low-power isolation config.
  * ISO_LATE is the most common setting. ISO_EARLY is only used when
  * an output pad is directly determined by another input pad. The
- * other two are only used when SW wants to directly contol isolation.
+ * other two are only used when SW wants to directly control isolation.
  */
 typedef uint8_t sc_pad_iso_t;
 
diff --git a/plat/imx/common/include/sci/svc/pm/sci_pm_api.h b/plat/imx/common/include/sci/svc/pm/sci_pm_api.h
index 76ca5c4ea..13647956a 100644
--- a/plat/imx/common/include/sci/svc/pm/sci_pm_api.h
+++ b/plat/imx/common/include/sci/svc/pm/sci_pm_api.h
@@ -294,7 +294,7 @@ sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
  * Note some resources are still not accessible even when powered up if bus
  * transactions go through a fabric not powered up. Examples of this are
  * resources in display and capture subsystems which require the display
- * controller or the imaging subsytem to be powered up first.
+ * controller or the imaging subsystem to be powered up first.
  *
  * Not that resources are grouped into power domains by the underlying
  * hardware. If any resource in the domain is on, the entire power domain
diff --git a/plat/imx/imx8m/gpc_common.c b/plat/imx/imx8m/gpc_common.c
index 32a35ef0b..71e0af1fd 100644
--- a/plat/imx/imx8m/gpc_common.c
+++ b/plat/imx/imx8m/gpc_common.c
@@ -98,7 +98,7 @@ void imx_set_cpu_lpm(unsigned int core_id, bool pdn)
 		/* assert the pcg pcr bit of the core */
 		mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
 	} else {
-		/* disbale CORE WFI PDN & IRQ PUP */
+		/* disable CORE WFI PDN & IRQ PUP */
 		mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |
 				COREx_IRQ_WUP(core_id));
 		/* deassert the pcg pcr bit of the core */
diff --git a/plat/imx/imx8m/imx8mm/gpc.c b/plat/imx/imx8m/imx8mm/gpc.c
index cc1cb1066..e0e38a9ae 100644
--- a/plat/imx/imx8m/imx8mm/gpc.c
+++ b/plat/imx/imx8m/imx8mm/gpc.c
@@ -376,7 +376,7 @@ void imx_gpc_init(void)
 	/*
 	 * Set the CORE & SCU power up timing:
 	 * SW = 0x1, SW2ISO = 0x1;
-	 * the CPU CORE and SCU power up timming counter
+	 * the CPU CORE and SCU power up timing counter
 	 * is drived  by 32K OSC, each domain's power up
 	 * latency is (SW + SW2ISO) / 32768
 	 */
diff --git a/plat/imx/imx8m/imx8mn/gpc.c b/plat/imx/imx8m/imx8mn/gpc.c
index 4e052972c..20c9a5561 100644
--- a/plat/imx/imx8m/imx8mn/gpc.c
+++ b/plat/imx/imx8m/imx8mn/gpc.c
@@ -170,7 +170,7 @@ void imx_gpc_init(void)
 	/*
 	 * Set the CORE & SCU power up timing:
 	 * SW = 0x1, SW2ISO = 0x1;
-	 * the CPU CORE and SCU power up timming counter
+	 * the CPU CORE and SCU power up timing counter
 	 * is drived  by 32K OSC, each domain's power up
 	 * latency is (SW + SW2ISO) / 32768
 	 */
diff --git a/plat/imx/imx8m/imx8mp/gpc.c b/plat/imx/imx8m/imx8mp/gpc.c
index 452e7883c..956b50817 100644
--- a/plat/imx/imx8m/imx8mp/gpc.c
+++ b/plat/imx/imx8m/imx8mp/gpc.c
@@ -337,7 +337,7 @@ void imx_gpc_init(void)
 	/*
 	 * Set the CORE & SCU power up timing:
 	 * SW = 0x1, SW2ISO = 0x1;
-	 * the CPU CORE and SCU power up timming counter
+	 * the CPU CORE and SCU power up timing counter
 	 * is drived  by 32K OSC, each domain's power up
 	 * latency is (SW + SW2ISO) / 32768
 	 */
diff --git a/plat/imx/imx8m/imx8mq/gpc.c b/plat/imx/imx8m/imx8mq/gpc.c
index 0a029d66c..ebf92f724 100644
--- a/plat/imx/imx8m/imx8mq/gpc.c
+++ b/plat/imx/imx8m/imx8mq/gpc.c
@@ -417,7 +417,7 @@ void imx_gpc_init(void)
 	/* set all mix/PU in A53 domain */
 	mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xfffd);
 
-	/* set SCU timming */
+	/* set SCU timing */
 	mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING,
 		      (0x59 << 10) | 0x5B | (0x2 << 20));
 
diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c
index 26ed7efc8..b4e19def9 100644
--- a/plat/intel/soc/agilex/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex/bl31_plat_setup.c
@@ -155,7 +155,7 @@ const mmap_region_t plat_agilex_mmap[] = {
 
 /*******************************************************************************
  * Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
+ * moment this is only initializes the mmu in a quick and dirty way.
  ******************************************************************************/
 void bl31_plat_arch_setup(void)
 {
diff --git a/plat/intel/soc/common/sip/socfpga_sip_fcs.c b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
index 508043ff7..d99026bcc 100644
--- a/plat/intel/soc/common/sip/socfpga_sip_fcs.c
+++ b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
@@ -1804,7 +1804,7 @@ int intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(uint32_t session_i
 
 	/*
 	 * Source data must be 4 bytes aligned
-	 * Source addrress must be 8 bytes aligned
+	 * Source address must be 8 bytes aligned
 	 * User data must be 8 bytes aligned
 	 */
 	if ((dst_size == NULL) || (mbox_error == NULL) ||
diff --git a/plat/intel/soc/n5x/bl31_plat_setup.c b/plat/intel/soc/n5x/bl31_plat_setup.c
index 5ca1a716e..a5337ceec 100644
--- a/plat/intel/soc/n5x/bl31_plat_setup.c
+++ b/plat/intel/soc/n5x/bl31_plat_setup.c
@@ -140,7 +140,7 @@ const mmap_region_t plat_dm_mmap[] = {
 
 /*******************************************************************************
  * Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
+ * moment this is only initializes the mmu in a quick and dirty way.
  ******************************************************************************/
 void bl31_plat_arch_setup(void)
 {
diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c
index be0fae563..ba00e8202 100644
--- a/plat/intel/soc/stratix10/bl31_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl31_plat_setup.c
@@ -147,7 +147,7 @@ const mmap_region_t plat_stratix10_mmap[] = {
 
 /*******************************************************************************
  * Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
+ * moment this is only initializes the mmu in a quick and dirty way.
  ******************************************************************************/
 void bl31_plat_arch_setup(void)
 {
diff --git a/plat/marvell/armada/a8k/common/plat_pm.c b/plat/marvell/armada/a8k/common/plat_pm.c
index 9ea927608..f08f08a35 100644
--- a/plat/marvell/armada/a8k/common/plat_pm.c
+++ b/plat/marvell/armada/a8k/common/plat_pm.c
@@ -423,7 +423,7 @@ static int a8k_pwr_domain_on(u_register_t mpidr)
 	} else
 #endif
 	{
-		/* proprietary CPU ON exection flow */
+		/* proprietary CPU ON execution flow */
 		plat_marvell_cpu_on(mpidr);
 	}
 	return 0;
diff --git a/plat/marvell/armada/common/marvell_ddr_info.c b/plat/marvell/armada/common/marvell_ddr_info.c
index 734099652..1ae0254b4 100644
--- a/plat/marvell/armada/common/marvell_ddr_info.c
+++ b/plat/marvell/armada/common/marvell_ddr_info.c
@@ -34,7 +34,7 @@
 	DRAM_AREA_LENGTH_MASK) >> DRAM_AREA_LENGTH_OFFS
 
 /* Mapping between DDR area length and real DDR size is specific and looks like
- * bellow:
+ * below:
  * 0 => 384 MB
  * 1 => 768 MB
  * 2 => 1536 MB
diff --git a/plat/mediatek/include/mtk_sip_svc.h b/plat/mediatek/include/mtk_sip_svc.h
index f67791572..684f95108 100644
--- a/plat/mediatek/include/mtk_sip_svc.h
+++ b/plat/mediatek/include/mtk_sip_svc.h
@@ -97,7 +97,7 @@ struct smc_descriptor {
 };
 
 /*
- * This function should be implemented in MediaTek SOC directory. It fullfills
+ * This function should be implemented in MediaTek SOC directory. It fulfills
  * MTK_SIP_SET_AUTHORIZED_SECURE_REG SiP call by checking the sreg with the
  * predefined secure register list, if a match was found, set val to sreg.
  *
diff --git a/plat/mediatek/mt8173/bl31_plat_setup.c b/plat/mediatek/mt8173/bl31_plat_setup.c
index bd7d0b0ee..fd7874fd0 100644
--- a/plat/mediatek/mt8173/bl31_plat_setup.c
+++ b/plat/mediatek/mt8173/bl31_plat_setup.c
@@ -129,7 +129,7 @@ void bl31_platform_setup(void)
 
 /*******************************************************************************
  * Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
+ * moment this is only initializes the mmu in a quick and dirty way.
  ******************************************************************************/
 void bl31_plat_arch_setup(void)
 {
diff --git a/plat/mediatek/mt8173/drivers/spm/spm.c b/plat/mediatek/mt8173/drivers/spm/spm.c
index 8980e075e..0d3acb268 100644
--- a/plat/mediatek/mt8173/drivers/spm/spm.c
+++ b/plat/mediatek/mt8173/drivers/spm/spm.c
@@ -20,7 +20,7 @@
  * - spm_suspend.c for system power control in system suspend scenario.
  *
  * This file provide utility functions common to hotplug, mcdi(idle), suspend
- * power scenarios. A bakery lock (software lock) is incoporated to protect
+ * power scenarios. A bakery lock (software lock) is incorporated to protect
  * certain critical sections to avoid kicking different SPM firmware
  * concurrently.
  */
diff --git a/plat/mediatek/mt8183/bl31_plat_setup.c b/plat/mediatek/mt8183/bl31_plat_setup.c
index 7dac8a49b..f608da3cf 100644
--- a/plat/mediatek/mt8183/bl31_plat_setup.c
+++ b/plat/mediatek/mt8183/bl31_plat_setup.c
@@ -163,7 +163,7 @@ void bl31_platform_setup(void)
 
 /*******************************************************************************
  * Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
+ * moment this is only initializes the mmu in a quick and dirty way.
  ******************************************************************************/
 void bl31_plat_arch_setup(void)
 {
diff --git a/plat/mediatek/mt8186/bl31_plat_setup.c b/plat/mediatek/mt8186/bl31_plat_setup.c
index 5fc6b6ea9..fb826befe 100644
--- a/plat/mediatek/mt8186/bl31_plat_setup.c
+++ b/plat/mediatek/mt8186/bl31_plat_setup.c
@@ -102,7 +102,7 @@ void bl31_platform_setup(void)
 
 /*******************************************************************************
  * Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
+ * moment this is only initializes the mmu in a quick and dirty way.
  ******************************************************************************/
 void bl31_plat_arch_setup(void)
 {
diff --git a/plat/mediatek/mt8192/bl31_plat_setup.c b/plat/mediatek/mt8192/bl31_plat_setup.c
index c3cb9a555..3b2302763 100644
--- a/plat/mediatek/mt8192/bl31_plat_setup.c
+++ b/plat/mediatek/mt8192/bl31_plat_setup.c
@@ -110,7 +110,7 @@ void bl31_platform_setup(void)
 
 /*******************************************************************************
  * Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
+ * moment this is only initializes the mmu in a quick and dirty way.
  ******************************************************************************/
 void bl31_plat_arch_setup(void)
 {
diff --git a/plat/mediatek/mt8195/bl31_plat_setup.c b/plat/mediatek/mt8195/bl31_plat_setup.c
index dff66709e..0f5674fd8 100644
--- a/plat/mediatek/mt8195/bl31_plat_setup.c
+++ b/plat/mediatek/mt8195/bl31_plat_setup.c
@@ -106,7 +106,7 @@ void bl31_platform_setup(void)
 
 /*******************************************************************************
  * Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
+ * moment this is only initializes the mmu in a quick and dirty way.
  ******************************************************************************/
 void bl31_plat_arch_setup(void)
 {
diff --git a/plat/mediatek/mt8195/drivers/apusys/apupll.c b/plat/mediatek/mt8195/drivers/apusys/apupll.c
index 0eb8d4a5c..3c18798c7 100644
--- a/plat/mediatek/mt8195/drivers/apusys/apupll.c
+++ b/plat/mediatek/mt8195/drivers/apusys/apupll.c
@@ -268,7 +268,7 @@ static int32_t _cal_pll_data(uint32_t *pd, uint32_t *dds, uint32_t freq)
  * @pll_idx: Which PLL to enable/disable
  * @on: 1 -> enable, 0 -> disable.
  *
- * This funciton will only change RG_PLL_EN of CON1 for pll[pll_idx].
+ * This function will only change RG_PLL_EN of CON1 for pll[pll_idx].
  *
  * Context: Any context.
  */
@@ -286,7 +286,7 @@ static void _pll_en(uint32_t pll_idx, bool on)
  * @pll_idx: Which PLL to enable/disable
  * @on: 1 -> enable, 0 -> disable.
  *
- * This funciton will only change PLL_SDM_PWR_ON of CON3 for pll[pll_idx].
+ * This function will only change PLL_SDM_PWR_ON of CON3 for pll[pll_idx].
  *
  * Context: Any context.
  */
@@ -304,7 +304,7 @@ static void _pll_pwr(uint32_t pll_idx, bool on)
  * @pll_idx: Which PLL to enable/disable
  * @enable: 1 -> turn on isolation, 0 -> turn off isolation.
  *
- * This funciton will turn on/off pll isolation by
+ * This function will turn on/off pll isolation by
  * changing PLL_SDM_PWR_ON of CON3 for pll[pll_idx].
  *
  * Context: Any context.
@@ -324,7 +324,7 @@ static void _pll_iso(uint32_t pll_idx, bool enable)
  * @on: 1 -> enable, 0 -> disable.
  * @fhctl_en: enable or disable fhctl function
  *
- * This is the entry poing for controlling pll and fhctl funciton on/off.
+ * This is the entry poing for controlling pll and fhctl function on/off.
  * Caller can chose only enable pll instead of fhctl function.
  *
  * Context: Any context.
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index 050ef52d9..e3068b699 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -262,7 +262,7 @@ void bl31_plat_runtime_setup(void)
 
 /*******************************************************************************
  * Perform the very early platform specific architectural setup here. At the
- * moment this only intializes the mmu in a quick and dirty way.
+ * moment this only initializes the mmu in a quick and dirty way.
  ******************************************************************************/
 void bl31_plat_arch_setup(void)
 {
diff --git a/plat/nvidia/tegra/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/drivers/memctrl/memctrl_v2.c
index 92120b527..0644fd203 100644
--- a/plat/nvidia/tegra/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/drivers/memctrl/memctrl_v2.c
@@ -301,7 +301,7 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
 	if (video_mem_base != 0U) {
 		/*
 		 * Lock the non overlapping memory being cleared so that
-		 * other masters do not accidently write to it. The memory
+		 * other masters do not accidentally write to it. The memory
 		 * would be unlocked once the non overlapping region is
 		 * cleared and the new memory settings take effect.
 		 */
diff --git a/plat/nvidia/tegra/include/drivers/tegra_gic.h b/plat/nvidia/tegra/include/drivers/tegra_gic.h
index 6661dff76..9f9477c0f 100644
--- a/plat/nvidia/tegra/include/drivers/tegra_gic.h
+++ b/plat/nvidia/tegra/include/drivers/tegra_gic.h
@@ -19,7 +19,7 @@ typedef struct pcpu_fiq_state {
 } pcpu_fiq_state_t;
 
 /*******************************************************************************
- * Fucntion declarations
+ * Function declarations
  ******************************************************************************/
 void tegra_gic_cpuif_deactivate(void);
 void tegra_gic_init(void);
diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h
index a971cec93..cf8778b26 100644
--- a/plat/nvidia/tegra/include/t186/tegra_def.h
+++ b/plat/nvidia/tegra/include/t186/tegra_def.h
@@ -84,7 +84,7 @@
 #define TEGRA_CLK_SE			TEGRA186_CLK_SE
 
 /*******************************************************************************
- * Tegra Miscellanous register constants
+ * Tegra Miscellaneous register constants
  ******************************************************************************/
 #define TEGRA_MISC_BASE			U(0x00100000)
 #define  HARDWARE_REVISION_OFFSET	U(0x4)
diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index abe193fcd..2158913be 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -60,7 +60,7 @@
 #define TEGRA_CLK_SE			TEGRA194_CLK_SE
 
 /*******************************************************************************
- * Tegra Miscellanous register constants
+ * Tegra Miscellaneous register constants
  ******************************************************************************/
 #define TEGRA_MISC_BASE			U(0x00100000)
 
diff --git a/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h b/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h
index ecfb3f4b3..45302da1b 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h
+++ b/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h
@@ -40,7 +40,7 @@ typedef enum {
 	/* index 83 is deprecated */
 	TEGRA_ARI_PERFMON = 84U,
 	TEGRA_ARI_UPDATE_CCPLEX_GSC = 85U,
-	/* index 86 is depracated */
+	/* index 86 is deprecated */
 	/* index 87 is deprecated */
 	TEGRA_ARI_ROC_FLUSH_CACHE_ONLY = 88U,
 	TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS = 89U,
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h
index 7a68a4303..ca74d2cf9 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h
@@ -17,7 +17,7 @@
 
 /**
  * Current version - Major version increments may break backwards
- * compatiblity and binary compatibility. Minor version increments
+ * compatibility and binary compatibility. Minor version increments
  * occur when there is only new functionality.
  */
 enum {
diff --git a/plat/nvidia/tegra/soc/t194/plat_ras.c b/plat/nvidia/tegra/soc/t194/plat_ras.c
index a9fed0ac7..6d7e90052 100644
--- a/plat/nvidia/tegra/soc/t194/plat_ras.c
+++ b/plat/nvidia/tegra/soc/t194/plat_ras.c
@@ -284,7 +284,7 @@ static int32_t tegra194_ras_node_handler(uint32_t errselr, const char *name,
 	ERROR("RAS Error in %s, ERRSELR_EL1=0x%x:\n", name, errselr);
 	ERROR("\tStatus = 0x%" PRIx64 "\n", status);
 
-	/* Print uncorrectable errror information. */
+	/* Print uncorrectable error information. */
 	if (ERR_STATUS_GET_FIELD(status, UE) != 0U) {
 
 		ERR_STATUS_SET_FIELD(val, UE, 1);
diff --git a/plat/nxp/common/setup/ls_bl31_setup.c b/plat/nxp/common/setup/ls_bl31_setup.c
index bd0ab4fb7..3d0d804c7 100644
--- a/plat/nxp/common/setup/ls_bl31_setup.c
+++ b/plat/nxp/common/setup/ls_bl31_setup.c
@@ -174,7 +174,7 @@ void bl31_platform_setup(void)
 	soc_platform_setup();
 
 	/* Console logs gone missing as part going to
-	 * EL1 for initilizing Bl32 if present.
+	 * EL1 for initializing Bl32 if present.
 	 * console flush is necessary to avoid it.
 	 */
 	(void)console_flush();
diff --git a/plat/nxp/soc-ls1088a/include/soc.h b/plat/nxp/soc-ls1088a/include/soc.h
index eb36c2e13..793feee5d 100644
--- a/plat/nxp/soc-ls1088a/include/soc.h
+++ b/plat/nxp/soc-ls1088a/include/soc.h
@@ -112,7 +112,7 @@
 #define IPSTPCR1_VALUE			0x000003FF
 #define IPSTPCR2_VALUE			0x00013006
 
-/* Dont' stop UART */
+/* Don't stop UART */
 #define IPSTPCR3_VALUE			0x0000033A
 
 #define IPSTPCR4_VALUE			0x00103300
diff --git a/plat/qti/common/src/qti_bl31_setup.c b/plat/qti/common/src/qti_bl31_setup.c
index dac025356..a5f58584d 100644
--- a/plat/qti/common/src/qti_bl31_setup.c
+++ b/plat/qti/common/src/qti_bl31_setup.c
@@ -81,7 +81,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 
 /*******************************************************************************
  * Perform the very early platform specific architectural setup here. At the
- * moment this only intializes the mmu in a quick and dirty way.
+ * moment this only initializes the mmu in a quick and dirty way.
  ******************************************************************************/
 void bl31_plat_arch_setup(void)
 {
diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c
index f85db8d65..9ec4bcdf0 100644
--- a/plat/renesas/rcar/bl2_plat_setup.c
+++ b/plat/renesas/rcar/bl2_plat_setup.c
@@ -1190,7 +1190,7 @@ static void bl2_init_generic_timer(void)
 		break;
 	}
 #endif /* RCAR_LSI == RCAR_E3 */
-	/* Update memory mapped and register based freqency */
+	/* Update memory mapped and register based frequency */
 	write_cntfrq_el0((u_register_t )reg_cntfid);
 	mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid);
 	/* Enable counter */
diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c
index 98ef415c9..59db3d85c 100644
--- a/plat/rockchip/common/bl31_plat_setup.c
+++ b/plat/rockchip/common/bl31_plat_setup.c
@@ -87,7 +87,7 @@ void bl31_platform_setup(void)
 
 /*******************************************************************************
  * Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
+ * moment this is only initializes the mmu in a quick and dirty way.
  ******************************************************************************/
 void bl31_plat_arch_setup(void)
 {
diff --git a/plat/rockchip/common/drivers/pmu/pmu_com.h b/plat/rockchip/common/drivers/pmu/pmu_com.h
index 5359f73b4..022bb024a 100644
--- a/plat/rockchip/common/drivers/pmu/pmu_com.h
+++ b/plat/rockchip/common/drivers/pmu/pmu_com.h
@@ -90,7 +90,7 @@ static int check_cpu_wfie(uint32_t cpu_id, uint32_t wfie_msk)
 
 	/*
 	 * wfe/wfi tracking not possible, hopefully the host
-	 * was sucessful in enabling wfe/wfi.
+	 * was successful in enabling wfe/wfi.
 	 * We'll give a bit of additional time, like the kernel does.
 	 */
 	if ((cluster_id && clstb_cpu_wfe < 0) ||
diff --git a/plat/rockchip/common/sp_min_plat_setup.c b/plat/rockchip/common/sp_min_plat_setup.c
index 0237b167f..8fb3f8ef1 100644
--- a/plat/rockchip/common/sp_min_plat_setup.c
+++ b/plat/rockchip/common/sp_min_plat_setup.c
@@ -82,7 +82,7 @@ void sp_min_platform_setup(void)
 
 /*******************************************************************************
  * Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
+ * moment this is only initializes the mmu in a quick and dirty way.
  ******************************************************************************/
 void sp_min_plat_arch_setup(void)
 {
diff --git a/plat/rockchip/rk3288/drivers/pmu/pmu.c b/plat/rockchip/rk3288/drivers/pmu/pmu.c
index d6d709887..085976c16 100644
--- a/plat/rockchip/rk3288/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3288/drivers/pmu/pmu.c
@@ -288,7 +288,7 @@ int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint)
 	/*
 	 * We communicate with the bootrom to active the cpus other
 	 * than cpu0, after a blob of initialize code, they will
-	 * stay at wfe state, once they are actived, they will check
+	 * stay at wfe state, once they are activated, they will check
 	 * the mailbox:
 	 * sram_base_addr + 4: 0xdeadbeaf
 	 * sram_base_addr + 8: start address for pc
diff --git a/plat/rockchip/rk3288/drivers/soc/soc.c b/plat/rockchip/rk3288/drivers/soc/soc.c
index 36f410b1a..2316fbebe 100644
--- a/plat/rockchip/rk3288/drivers/soc/soc.c
+++ b/plat/rockchip/rk3288/drivers/soc/soc.c
@@ -216,7 +216,7 @@ void __dead2 rockchip_soc_soft_reset(void)
 
 	/*
 	 * Maybe the HW needs some times to reset the system,
-	 * so we do not hope the core to excute valid codes.
+	 * so we do not hope the core to execute valid codes.
 	 */
 	while (1)
 		;
diff --git a/plat/rockchip/rk3328/drivers/pmu/pmu.c b/plat/rockchip/rk3328/drivers/pmu/pmu.c
index a17fef9e1..597db978f 100644
--- a/plat/rockchip/rk3328/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3328/drivers/pmu/pmu.c
@@ -202,7 +202,7 @@ void __dead2 rockchip_soc_soft_reset(void)
 	dsb();
 	/*
 	 * Maybe the HW needs some times to reset the system,
-	 * so we do not hope the core to excute valid codes.
+	 * so we do not hope the core to execute valid codes.
 	 */
 	while (1)
 		;
@@ -210,7 +210,7 @@ void __dead2 rockchip_soc_soft_reset(void)
 
 /*
  * For PMIC RK805, its sleep pin is connect with gpio2_d2 from rk3328.
- * If the PMIC is configed for responding the sleep pin to power off it,
+ * If the PMIC is configured for responding the sleep pin to power off it,
  * once the pin is output high,  it will get the pmic power off.
  */
 void __dead2 rockchip_soc_system_off(void)
@@ -462,7 +462,7 @@ static __sramfunc void sram_udelay(uint32_t us)
 
 /*
  * For PMIC RK805, its sleep pin is connect with gpio2_d2 from rk3328.
- * If the PMIC is configed for responding the sleep pin
+ * If the PMIC is configured for responding the sleep pin
  * to get it into sleep mode,
  * once the pin is output high,  it will get the pmic into sleep mode.
  */
diff --git a/plat/rockchip/rk3328/drivers/soc/soc.h b/plat/rockchip/rk3328/drivers/soc/soc.h
index e8cbc09f6..e081f7171 100644
--- a/plat/rockchip/rk3328/drivers/soc/soc.h
+++ b/plat/rockchip/rk3328/drivers/soc/soc.h
@@ -27,7 +27,7 @@ enum plls_id {
 	DPLL_ID,
 	CPLL_ID,
 	GPLL_ID,
-	REVERVE,
+	RESERVE,
 	NPLL_ID,
 	MAX_PLL,
 };
diff --git a/plat/rockchip/rk3368/drivers/soc/soc.c b/plat/rockchip/rk3368/drivers/soc/soc.c
index 7d51bb8e8..9bb237f80 100644
--- a/plat/rockchip/rk3368/drivers/soc/soc.c
+++ b/plat/rockchip/rk3368/drivers/soc/soc.c
@@ -202,7 +202,7 @@ void __dead2 rockchip_soc_soft_reset(void)
 
 	/*
 	 * Maybe the HW needs some times to reset the system,
-	 * so we do not hope the core to excute valid codes.
+	 * so we do not hope the core to execute valid codes.
 	 */
 	while (1)
 	;
diff --git a/plat/rockchip/rk3399/drivers/dram/dfs.c b/plat/rockchip/rk3399/drivers/dram/dfs.c
index 816372bfc..11b0373a7 100644
--- a/plat/rockchip/rk3399/drivers/dram/dfs.c
+++ b/plat/rockchip/rk3399/drivers/dram/dfs.c
@@ -1696,7 +1696,7 @@ static int to_get_clk_index(unsigned int mhz)
 
 	pll_cnt = ARRAY_SIZE(dpll_rates_table);
 
-	/* Assumming rate_table is in descending order */
+	/* Assuming rate_table is in descending order */
 	for (i = 0; i < pll_cnt; i++) {
 		if (mhz >= dpll_rates_table[i].mhz)
 			break;
diff --git a/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h b/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h
index 9cda22ca9..102ba789f 100644
--- a/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h
+++ b/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h
@@ -103,7 +103,7 @@ struct dram_timing_t {
 	uint32_t tcksre;
 	uint32_t tcksrx;
 	uint32_t tdpd;
-	/* mode regiter timing */
+	/* mode register timing */
 	uint32_t tmod;
 	uint32_t tmrd;
 	uint32_t tmrr;
diff --git a/plat/rockchip/rk3399/drivers/dram/suspend.c b/plat/rockchip/rk3399/drivers/dram/suspend.c
index a8b1c32d5..caa784c79 100644
--- a/plat/rockchip/rk3399/drivers/dram/suspend.c
+++ b/plat/rockchip/rk3399/drivers/dram/suspend.c
@@ -561,7 +561,7 @@ static __pmusramfunc int dram_switch_to_next_index(
 
 	ch_count = sdram_params->num_channels;
 
-	/* LPDDR4 f2 cann't do training, all training will fail */
+	/* LPDDR4 f2 can't do training, all training will fail */
 	for (ch = 0; ch < ch_count; ch++) {
 		/*
 		 * Without this disabled for LPDDR4 we end up writing 0's
diff --git a/plat/rockchip/rk3399/drivers/m0/src/suspend.c b/plat/rockchip/rk3399/drivers/m0/src/suspend.c
index 9ad2fa26a..8a0ea32ab 100644
--- a/plat/rockchip/rk3399/drivers/m0/src/suspend.c
+++ b/plat/rockchip/rk3399/drivers/m0/src/suspend.c
@@ -30,7 +30,7 @@ __attribute__((noreturn)) void m0_main(void)
 	}
 
 	/*
-	 * FSM power secquence is .. -> ST_INPUT_CLAMP(step.17) -> .. ->
+	 * FSM power sequence is .. -> ST_INPUT_CLAMP(step.17) -> .. ->
 	 * ST_WAKEUP_RESET -> ST_EXT_PWRUP-> ST_RELEASE_CLAMP ->
 	 * ST_24M_OSC_EN -> .. -> ST_WAKEUP_RESET_CLR(step.26) -> ..,
 	 * INPUT_CLAMP and WAKEUP_RESET will hold the SOC not affect by
diff --git a/plat/rockchip/rk3399/drivers/secure/secure.h b/plat/rockchip/rk3399/drivers/secure/secure.h
index e31c999b7..79997b2f6 100644
--- a/plat/rockchip/rk3399/drivers/secure/secure.h
+++ b/plat/rockchip/rk3399/drivers/secure/secure.h
@@ -32,7 +32,7 @@
 /* security config pmu slave ip */
 /* All of slaves  is ns */
 #define SGRF_PMU_SLV_S_NS		BIT_WITH_WMSK(0)
-/* slaves secure attr is configed */
+/* slaves secure attr is configured */
 #define SGRF_PMU_SLV_S_CFGED		WMSK_BIT(0)
 #define SGRF_PMU_SLV_CRYPTO1_NS		WMSK_BIT(1)
 
diff --git a/plat/rockchip/rk3399/drivers/soc/soc.c b/plat/rockchip/rk3399/drivers/soc/soc.c
index 98b5ad646..e2b2934b0 100644
--- a/plat/rockchip/rk3399/drivers/soc/soc.c
+++ b/plat/rockchip/rk3399/drivers/soc/soc.c
@@ -343,7 +343,7 @@ void __dead2 soc_global_soft_reset(void)
 
 	/*
 	 * Maybe the HW needs some times to reset the system,
-	 * so we do not hope the core to excute valid codes.
+	 * so we do not hope the core to execute valid codes.
 	 */
 	while (1)
 		;
diff --git a/plat/rpi/rpi4/rpi4_pci_svc.c b/plat/rpi/rpi4/rpi4_pci_svc.c
index 7d1ca5c6e..e4ef5c1ae 100644
--- a/plat/rpi/rpi4/rpi4_pci_svc.c
+++ b/plat/rpi/rpi4/rpi4_pci_svc.c
@@ -11,7 +11,7 @@
  * it. Given that it's not ECAM compliant yet reasonably simple, it makes for
  * an excellent example of the PCI SMCCC interface.
  *
- * The PCI SMCCC interface is described in DEN0115 availabe from:
+ * The PCI SMCCC interface is described in DEN0115 available from:
  * https://developer.arm.com/documentation/den0115/latest
  */
 
diff --git a/plat/st/stm32mp1/stm32mp1_pm.c b/plat/st/stm32mp1/stm32mp1_pm.c
index 74393811c..8e1c1cf99 100644
--- a/plat/st/stm32mp1/stm32mp1_pm.c
+++ b/plat/st/stm32mp1/stm32mp1_pm.c
@@ -42,7 +42,7 @@ static void stm32_cpu_standby(plat_local_state_t cpu_state)
 	while (interrupt == GIC_SPURIOUS_INTERRUPT) {
 		wfi();
 
-		/* Acknoledge IT */
+		/* Acknowledge IT */
 		interrupt = gicv2_acknowledge_interrupt();
 		/* If Interrupt == 1022 it will be acknowledged by non secure */
 		if ((interrupt != PENDING_G1_INTID) &&
diff --git a/plat/xilinx/common/plat_startup.c b/plat/xilinx/common/plat_startup.c
index 6a83e9e3f..539aba2a9 100644
--- a/plat/xilinx/common/plat_startup.c
+++ b/plat/xilinx/common/plat_startup.c
@@ -135,7 +135,7 @@ static int32_t get_fsbl_estate(const struct xfsbl_partition *partition)
  * @bl33:	BL33 image info structure
  * atf_handoff_addr:  ATF handoff address
  *
- * Process the handoff paramters from the FSBL and populate the BL32 and BL33
+ * Process the handoff parameters from the FSBL and populate the BL32 and BL33
  * image info structures accordingly.
  *
  * Return: Return the status of the handoff. The value will be from the
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
index fb7b00924..85e146448 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
@@ -635,7 +635,7 @@ enum pm_ret_status pm_get_chipid(uint32_t *value)
  * pm_secure_rsaaes() - Load the secure images.
  *
  * This function provides access to the xilsecure library to load
- * the authenticated, encrypted, and authenicated/encrypted images.
+ * the authenticated, encrypted, and authenticated/encrypted images.
  *
  * address_low: lower 32-bit Linear memory space address
  *
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
index c0c5d1497..7b1544391 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
@@ -99,7 +99,7 @@ static void trigger_wdt_restart(void)
  * for warm restart.
  *
  * In presence of non-secure software layers (EL1/2) sets the interrupt
- * at registered entrance in GIC and informs that PMU responsed or demands
+ * at registered entrance in GIC and informs that PMU responded or demands
  * action.
  */
 static uint64_t ttc_fiq_handler(uint32_t id, uint32_t flags, void *handle,
diff --git a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
index b51369a02..eaecb899e 100644
--- a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
+++ b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
@@ -43,7 +43,7 @@ void tsp_platform_setup(void)
 
 /*******************************************************************************
  * Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the MMU
+ * moment this is only initializes the MMU
  ******************************************************************************/
 void tsp_plat_arch_setup(void)
 {