diff options
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | common/feat_detect.c | 12 | ||||
| -rw-r--r-- | docs/getting_started/build-options.rst | 11 | ||||
| -rw-r--r-- | include/arch/aarch64/arch_features.h | 5 |
4 files changed, 9 insertions, 21 deletions
@@ -1090,6 +1090,7 @@ $(eval $(call assert_booleans,\ ENABLE_AMU_FCONF \ AMU_RESTRICT_COUNTERS \ ENABLE_ASSERTIONS \ + ENABLE_FEAT_SB \ ENABLE_PIE \ ENABLE_PMF \ ENABLE_PSCI_STAT \ @@ -1174,7 +1175,6 @@ $(eval $(call assert_numerics,\ ENABLE_FEAT_PAN \ ENABLE_FEAT_RNG \ ENABLE_FEAT_RNG_TRAP \ - ENABLE_FEAT_SB \ ENABLE_FEAT_SEL2 \ ENABLE_FEAT_TCR2 \ ENABLE_FEAT_VHE \ diff --git a/common/feat_detect.c b/common/feat_detect.c index 7a6c9193e..4b5dcd462 100644 --- a/common/feat_detect.c +++ b/common/feat_detect.c @@ -60,16 +60,6 @@ check_feature(int state, unsigned long field, const char *feat_name, } } -/****************************************** - * Feature : FEAT_SB (Speculation Barrier) - *****************************************/ -static void read_feat_sb(void) -{ -#if (ENABLE_FEAT_SB == FEAT_STATE_ALWAYS) - feat_detect_panic(is_armv8_0_feat_sb_present(), "SB"); -#endif -} - /****************************************************** * Feature : FEAT_CSV2_2 (Cache Speculation Variant 2) *****************************************************/ @@ -256,7 +246,7 @@ void detect_arch_features(void) tainted = false; /* v8.0 features */ - read_feat_sb(); + check_feature(ENABLE_FEAT_SB, read_feat_sb_id_field(), "SB", 1, 1); read_feat_csv2_2(); /* v8.1 features */ diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index 94c12defe..0540b6d2f 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -327,12 +327,11 @@ Common build options Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from Armv8.5 onwards. -- ``ENABLE_FEAT_SB``: Numeric value to enable the ``FEAT_SB`` (Speculation - Barrier) extension allowing access to ``sb`` instruction. ``FEAT_SB`` is an - optional feature and defaults to ``0`` for pre-Armv8.5 CPUs but are mandatory - for Armv8.5 or later CPUs. This flag can take values 0 to 2, to align with - ``FEATURE_DETECTION`` mechanism. It is enabled from v8.5 and upwards and if - needed could be overidden from platforms explicitly. Default value is ``0``. +- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB`` + (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and + defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or + later CPUs. It is enabled from v8.5 and upwards and if needed can be + overidden from platforms explicitly. - ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h index ad938aea3..1af775876 100644 --- a/include/arch/aarch64/arch_features.h +++ b/include/arch/aarch64/arch_features.h @@ -256,10 +256,9 @@ static inline unsigned int get_armv9_2_feat_rme_support(void) /********************************************************************************* * Function to identify the presence of FEAT_SB (Speculation Barrier Instruction) ********************************************************************************/ -static inline bool is_armv8_0_feat_sb_present(void) +static inline unsigned int read_feat_sb_id_field(void) { - return (((read_id_aa64isar1_el1() >> ID_AA64ISAR1_SB_SHIFT) & - ID_AA64ISAR1_SB_MASK) == ID_AA64ISAR1_SB_SUPPORTED); + return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB); } /********************************************************************************* |