diff options
| -rw-r--r-- | Makefile | 9 | ||||
| -rw-r--r-- | bl31/bl31.mk | 4 | ||||
| -rw-r--r-- | docs/getting_started/build-options.rst | 24 | ||||
| -rw-r--r-- | drivers/arm/gic/v3/gicv3_main.c | 2 | ||||
| -rw-r--r-- | lib/el3_runtime/aarch64/context_mgmt.c | 41 | ||||
| -rw-r--r-- | lib/extensions/sme/sme.c | 3 | ||||
| -rw-r--r-- | make_helpers/defaults.mk | 8 |
7 files changed, 44 insertions, 47 deletions
@@ -916,11 +916,20 @@ ifeq (${ENABLE_RME},1) endif endif +ifneq (${ENABLE_SME_FOR_NS},0) + ifeq (${ENABLE_SVE_FOR_NS},0) + $(error "ENABLE_SME_FOR_NS requires ENABLE_SVE_FOR_NS") + endif +endif + # Secure SME/SVE requires the non-secure component as well ifeq (${ENABLE_SME_FOR_SWD},1) ifeq (${ENABLE_SME_FOR_NS},0) $(error "ENABLE_SME_FOR_SWD requires ENABLE_SME_FOR_NS") endif + ifeq (${ENABLE_SVE_FOR_SWD},0) + $(error "ENABLE_SME_FOR_SWD requires ENABLE_SVE_FOR_SWD") + endif endif ifeq (${ENABLE_SVE_FOR_SWD},1) ifeq (${ENABLE_SVE_FOR_NS},0) diff --git a/bl31/bl31.mk b/bl31/bl31.mk index 9b5cf55bc..b16b4e79b 100644 --- a/bl31/bl31.mk +++ b/bl31/bl31.mk @@ -101,12 +101,10 @@ endif ifneq (${ENABLE_SME_FOR_NS},0) BL31_SOURCES += lib/extensions/sme/sme.c -BL31_SOURCES += lib/extensions/sve/sve.c -else +endif ifneq (${ENABLE_SVE_FOR_NS},0) BL31_SOURCES += lib/extensions/sve/sve.c endif -endif ifneq (${ENABLE_MPAM_FOR_LOWER_ELS},0) BL31_SOURCES += lib/extensions/mpam/mpam.c diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index 2735f173f..ffde0a409 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -436,7 +436,8 @@ Common build options (SME), SVE, and FPU/SIMD for the non-secure world only. These features share registers so are enabled together. Using this option without ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure - world to trap to EL3. SME is an optional architectural feature for AArch64 + world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a + superset of SVE. SME is an optional architectural feature for AArch64 and TF-A support is experimental. At this time, this build option cannot be used on systems that have SPD=spmd/SPM_MM or ENABLE_RME, and attempting to build with these options will fail. This flag can take the values 0 to 2, to @@ -450,10 +451,9 @@ Common build options align with the ``FEATURE_DETECTION`` mechanism. Default is 0. - ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix - Extension for secure world use along with SVE and FPU/SIMD, ENABLE_SME_FOR_NS - must also be set to use this. If enabling this, the secure world MUST - handle context switching for SME, SVE, and FPU/SIMD registers to ensure that - no data is leaked to non-secure world. This is experimental. Default is 0. + Extension for secure world. Used along with SVE and FPU/SIMD. + ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. + This is experimental. Default is 0. - ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling extensions. This is an optional architectural feature for AArch64. @@ -469,17 +469,15 @@ Common build options This is to avoid corruption of the Non-secure world data in the Z-registers which are aliased by the SIMD and FP registers. The build option is not compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an - assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` enabled. - This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` - mechanism. The default is 2 but is automatically disabled when - ENABLE_SME_FOR_NS is enabled ( set to 1 or 2) since SME encompasses SVE. - At this time, this build option cannot be used on systems that have SPM_MM - enabled. + assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` + enabled. This flag can take the values 0 to 2, to align with the + ``FEATURE_DETECTION`` mechanism. At this time, this build option cannot be + used on systems that have SPM_MM enabled. The default is 1. - ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. SVE is an optional architectural feature for AArch64. Note that this option - requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it - is automatically disabled when the target architecture is AArch32. + requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is + automatically disabled when the target architecture is AArch32. - ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection checks in GCC. Allowed values are "all", "strong", "default" and "none". The diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c index 168d0ebc9..2c7480001 100644 --- a/drivers/arm/gic/v3/gicv3_main.c +++ b/drivers/arm/gic/v3/gicv3_main.c @@ -330,6 +330,8 @@ void gicv3_cpuif_enable(unsigned int proc_num) /* Enable Group1 Secure interrupts */ write_icc_igrpen1_el3(read_icc_igrpen1_el3() | IGRPEN1_EL3_ENABLE_G1S_BIT); + /* and restore the original */ + write_scr_el3(scr_el3); isb(); /* Add DSB to ensure visibility of System register writes */ dsb(); diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index e38b34dcd..744e4f910 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -517,12 +517,13 @@ static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) amu_enable(el2_unused, ctx); } - /* Enable SME, SVE, and FPU/SIMD for non-secure world. */ + /* Enable SVE and FPU/SIMD */ + if (is_feat_sve_supported()) { + sve_enable(ctx); + } + if (is_feat_sme_supported()) { sme_enable(ctx); - } else if (is_feat_sve_supported()) { - /* Enable SVE and FPU/SIMD for non-secure world. */ - sve_enable(ctx); } if (is_feat_mpam_supported()) { @@ -553,22 +554,7 @@ static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) static void manage_extensions_secure(cpu_context_t *ctx) { #if IMAGE_BL31 - - if (is_feat_sme_supported()) { - if (ENABLE_SME_FOR_SWD) { - /* - * Enable SME, SVE, FPU/SIMD in secure context, secure manager - * must ensure SME, SVE, and FPU/SIMD context properly managed. - */ - sme_enable(ctx); - } else { - /* - * Disable SME, SVE, FPU/SIMD in secure context so non-secure - * world can safely use the associated registers. - */ - sme_disable(ctx); - } - } else if (is_feat_sve_supported()) { + if (is_feat_sve_supported()) { if (ENABLE_SVE_FOR_SWD) { /* * Enable SVE and FPU in secure context, secure manager must @@ -585,6 +571,21 @@ static void manage_extensions_secure(cpu_context_t *ctx) } } + if (is_feat_sme_supported()) { + if (ENABLE_SME_FOR_SWD) { + /* + * Enable SME, SVE, FPU/SIMD in secure context, secure manager + * must ensure SME, SVE, and FPU/SIMD context properly managed. + */ + sme_enable(ctx); + } else { + /* + * Disable SME, SVE, FPU/SIMD in secure context so non-secure + * world can safely use the associated registers. + */ + sme_disable(ctx); + } + } #endif /* IMAGE_BL31 */ } diff --git a/lib/extensions/sme/sme.c b/lib/extensions/sme/sme.c index f888d12c4..3423dbaf5 100644 --- a/lib/extensions/sme/sme.c +++ b/lib/extensions/sme/sme.c @@ -65,9 +65,6 @@ void sme_enable(cpu_context_t *context) /* Reset CPTR_EL3 value. */ write_cptr_el3(cptr_el3); isb(); - - /* Enable SVE/FPU in addition to SME. */ - sve_enable(context); } void sme_disable(cpu_context_t *context) diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index 8ec16fa60..e2a67f7ac 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -401,14 +401,6 @@ SVE_VECTOR_LEN := 2048 # SME defaults to disabled ENABLE_SME_FOR_NS := 0 ENABLE_SME_FOR_SWD := 0 - -# If SME is enabled then force SVE off -ifneq (${ENABLE_SME_FOR_NS},0) - override ENABLE_SVE_FOR_NS := 0 - override ENABLE_SVE_FOR_SWD := 0 -endif - -# SME2 defaults to disabled ENABLE_SME2_FOR_NS := 0 SANITIZE_UB := off |