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-rw-r--r--common/feat_detect.c15
-rw-r--r--include/arch/aarch64/arch.h1
-rw-r--r--include/arch/aarch64/arch_features.h18
-rw-r--r--include/arch/aarch64/arch_helpers.h1
-rw-r--r--include/lib/el3_runtime/aarch64/context.h4
-rw-r--r--lib/el3_runtime/aarch64/context.S24
-rw-r--r--lib/el3_runtime/aarch64/context_mgmt.c16
-rw-r--r--plat/arm/board/fvp/platform.mk1
8 files changed, 30 insertions, 50 deletions
diff --git a/common/feat_detect.c b/common/feat_detect.c
index b335a610f..1c505e211 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -90,18 +90,6 @@ static void read_feat_dit(void)
#endif
}
-/**************************************************************
- * Feature : FEAT_NV2 (Enhanced Nested Virtualization Support)
- *************************************************************/
-static void read_feat_nv2(void)
-{
-#if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_ALWAYS)
- unsigned int nv = get_armv8_4_feat_nv_support();
-
- feat_detect_panic((nv == ID_AA64MMFR2_EL1_NV2_SUPPORTED), "NV2");
-#endif
-}
-
/***********************************
* Feature : FEAT_SEL2 (Secure EL2)
**********************************/
@@ -223,7 +211,8 @@ void detect_arch_features(void)
"AMUv1", 1, 2);
check_feature(ENABLE_MPAM_FOR_LOWER_ELS, read_feat_mpam_version(),
"MPAM", 1, 17);
- read_feat_nv2();
+ check_feature(CTX_INCLUDE_NEVE_REGS, read_feat_nv_id_field(),
+ "NV2", 2, 2);
read_feat_sel2();
check_feature(ENABLE_TRF_FOR_NS, read_feat_trf_id_field(),
"TRF", 1, 1);
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 58abd449e..8663ab8e7 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -119,6 +119,7 @@
#define MPAMVPM7_EL2 S3_4_C10_C6_7
#define MPAMVPMV_EL2 S3_4_C10_C4_1
#define TRFCR_EL2 S3_4_C1_C2_1
+#define VNCR_EL2 S3_4_C2_C2_0
#define PMSCR_EL2 S3_4_C9_C9_0
#define TFSR_EL2 S3_4_C5_C6_0
#define CONTEXTIDR_EL2 S3_4_C13_C0_1
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index fa8015476..72927fbf9 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -423,10 +423,22 @@ static inline bool is_feat_trf_supported(void)
* Function to identify the presence of FEAT_NV2 (Enhanced Nested Virtualization
* Support)
*******************************************************************************/
-static inline unsigned int get_armv8_4_feat_nv_support(void)
+static inline unsigned int read_feat_nv_id_field(void)
{
- return (((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_NV_SHIFT) &
- ID_AA64MMFR2_EL1_NV_MASK));
+ return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_NV);
+}
+
+static inline bool is_feat_nv2_supported(void)
+{
+ if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_DISABLED) {
+ return false;
+ }
+
+ if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_ALWAYS) {
+ return true;
+ }
+
+ return read_feat_nv_id_field() >= ID_AA64MMFR2_EL1_NV2_SUPPORTED;
}
/*******************************************************************************
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 35027ca67..04b64be5c 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -573,6 +573,7 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(dit, DIT)
/* Armv8.4 FEAT_TRF Register */
DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el2, TRFCR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(vncr_el2, VNCR_EL2)
/* Armv8.5 MTE Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1)
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index e70ff99fa..e5e7e7422 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -521,10 +521,6 @@ void el2_sysregs_context_restore_mte(el2_sysregs_t *regs);
void el2_sysregs_context_save_ras(el2_sysregs_t *regs);
void el2_sysregs_context_restore_ras(el2_sysregs_t *regs);
#endif /* RAS_EXTENSION */
-#if CTX_INCLUDE_NEVE_REGS
-void el2_sysregs_context_save_nv2(el2_sysregs_t *regs);
-void el2_sysregs_context_restore_nv2(el2_sysregs_t *regs);
-#endif /* CTX_INCLUDE_NEVE_REGS */
#endif /* CTX_INCLUDE_EL2_REGS */
#if CTX_INCLUDE_FPREGS
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 715406487..013a505d4 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -21,10 +21,6 @@
.global el2_sysregs_context_save_ras
.global el2_sysregs_context_restore_ras
#endif /* RAS_EXTENSION */
-#if CTX_INCLUDE_NEVE_REGS
- .global el2_sysregs_context_save_nv2
- .global el2_sysregs_context_restore_nv2
-#endif /* CTX_INCLUDE_NEVE_REGS */
#endif /* CTX_INCLUDE_EL2_REGS */
.global el1_sysregs_context_save
@@ -238,26 +234,6 @@ func el2_sysregs_context_restore_ras
endfunc el2_sysregs_context_restore_ras
#endif /* RAS_EXTENSION */
-#if CTX_INCLUDE_NEVE_REGS
-func el2_sysregs_context_save_nv2
- /*
- * VNCR_EL2 register is saved only when FEAT_NV2 is supported.
- */
- mrs x16, vncr_el2
- str x16, [x0, #CTX_VNCR_EL2]
- ret
-endfunc el2_sysregs_context_save_nv2
-
-func el2_sysregs_context_restore_nv2
- /*
- * VNCR_EL2 register is restored only when FEAT_NV2 is supported.
- */
- ldr x16, [x0, #CTX_VNCR_EL2]
- msr vncr_el2, x16
- ret
-endfunc el2_sysregs_context_restore_nv2
-#endif /* CTX_INCLUDE_NEVE_REGS */
-
#endif /* CTX_INCLUDE_EL2_REGS */
/* ------------------------------------------------------------------
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 8f46b80dc..2ba2f9ce2 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -970,9 +970,12 @@ void cm_el2_sysregs_context_save(uint32_t security_state)
#if RAS_EXTENSION
el2_sysregs_context_save_ras(el2_sysregs_ctx);
#endif
-#if CTX_INCLUDE_NEVE_REGS
- el2_sysregs_context_save_nv2(el2_sysregs_ctx);
-#endif
+
+ if (is_feat_nv2_supported()) {
+ write_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2,
+ read_vncr_el2());
+ }
+
if (is_feat_trf_supported()) {
write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2());
}
@@ -1036,9 +1039,10 @@ void cm_el2_sysregs_context_restore(uint32_t security_state)
#if RAS_EXTENSION
el2_sysregs_context_restore_ras(el2_sysregs_ctx);
#endif
-#if CTX_INCLUDE_NEVE_REGS
- el2_sysregs_context_restore_nv2(el2_sysregs_ctx);
-#endif
+
+ if (is_feat_nv2_supported()) {
+ write_vncr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2));
+ }
if (is_feat_trf_supported()) {
write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2));
}
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index a6f8eaf64..ef62e731b 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -470,6 +470,7 @@ ENABLE_FEAT_FGT := 2
ENABLE_FEAT_HCX := 2
ENABLE_FEAT_TCR2 := 2
+CTX_INCLUDE_NEVE_REGS := 2
ENABLE_FEAT_CSV2_2 := 2
ENABLE_FEAT_ECV := 2
ENABLE_FEAT_PAN := 2
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