diff options
57 files changed, 135 insertions, 135 deletions
diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S index 124358cbb..bec234b1e 100644 --- a/bl1/bl1.ld.S +++ b/bl1/bl1.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -72,7 +72,7 @@ SECTIONS { . = ALIGN(16); } >ROM #else /* SEPARATE_CODE_AND_RODATA */ - ro . : { + .ro . : { __RO_START__ = .; *bl1_entrypoint.o(.text*) @@ -118,9 +118,9 @@ SECTIONS { * not mixed with normal data. This is required to set up the correct memory * attributes for the coherent data page tables. */ - coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { + .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { __COHERENT_RAM_START__ = .; - *(tzfw_coherent_mem) + *(.tzfw_coherent_mem) __COHERENT_RAM_END_UNALIGNED__ = .; /* diff --git a/bl2/bl2.ld.S b/bl2/bl2.ld.S index 3df8f07eb..458a12b92 100644 --- a/bl2/bl2.ld.S +++ b/bl2/bl2.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -60,7 +60,7 @@ SECTIONS { __RODATA_END__ = .; } >RAM #else /* SEPARATE_CODE_AND_RODATA */ - ro . : { + .ro . : { __RO_START__ = .; *bl2_entrypoint.o(.text*) @@ -98,9 +98,9 @@ SECTIONS { * not mixed with normal data. This is required to set up the correct * memory attributes for the coherent data page tables. */ - coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { + .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { __COHERENT_RAM_START__ = .; - *(tzfw_coherent_mem) + *(.tzfw_coherent_mem) __COHERENT_RAM_END_UNALIGNED__ = .; /* diff --git a/bl2/bl2_el3.ld.S b/bl2/bl2_el3.ld.S index 0c2764eb9..aa457faf4 100644 --- a/bl2/bl2_el3.ld.S +++ b/bl2/bl2_el3.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -76,7 +76,7 @@ SECTIONS { ASSERT(__TEXT_RESIDENT_END__ - __TEXT_RESIDENT_START__ <= PAGE_SIZE, "Resident part of BL2 has exceeded its limit.") #else /* SEPARATE_CODE_AND_RODATA */ - ro . : { + .ro . : { __RO_START__ = .; __TEXT_RESIDENT_START__ = .; @@ -149,10 +149,10 @@ SECTIONS { * not mixed with normal data. This is required to set up the correct * memory attributes for the coherent data page tables. */ - coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { + .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { __COHERENT_RAM_START__ = .; - *(tzfw_coherent_mem) + *(.tzfw_coherent_mem) __COHERENT_RAM_END_UNALIGNED__ = .; diff --git a/bl2u/bl2u.ld.S b/bl2u/bl2u.ld.S index 0f06dfd7b..52a925bd4 100644 --- a/bl2u/bl2u.ld.S +++ b/bl2u/bl2u.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -55,7 +55,7 @@ SECTIONS { __RODATA_END__ = .; } >RAM #else /* SEPARATE_CODE_AND_RODATA */ - ro . : { + .ro . : { __RO_START__ = .; *bl2u_entrypoint.o(.text*) @@ -93,9 +93,9 @@ SECTIONS { * not mixed with normal data. This is required to set up the correct * memory attributes for the coherent data page tables. */ - coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { + .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { __COHERENT_RAM_START__ = .; - *(tzfw_coherent_mem) + *(.tzfw_coherent_mem) __COHERENT_RAM_END_UNALIGNED__ = .; /* diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index 5d3139b60..c8290587e 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -66,7 +66,7 @@ SECTIONS { __RODATA_END__ = .; } >RAM #else /* SEPARATE_CODE_AND_RODATA */ - ro . : { + .ro . : { __RO_START__ = .; *bl31_entrypoint.o(.text*) @@ -111,7 +111,7 @@ SECTIONS { * There's no need to include this into the RO section of BL31 because it * doesn't need to be accessed by BL31. */ - spm_shim_exceptions : ALIGN(PAGE_SIZE) { + .spm_shim_exceptions : ALIGN(PAGE_SIZE) { __SPM_SHIM_EXCEPTIONS_START__ = .; *(.spm_shim_exceptions) @@ -121,9 +121,9 @@ SECTIONS { __SPM_SHIM_EXCEPTIONS_END__ = .; } >SPM_SHIM_EXCEPTIONS_VMA AT>RAM - PROVIDE(__SPM_SHIM_EXCEPTIONS_LMA__ = LOADADDR(spm_shim_exceptions)); + PROVIDE(__SPM_SHIM_EXCEPTIONS_LMA__ = LOADADDR(.spm_shim_exceptions)); - . = LOADADDR(spm_shim_exceptions) + SIZEOF(spm_shim_exceptions); + . = LOADADDR(.spm_shim_exceptions) + SIZEOF(.spm_shim_exceptions); #endif /* SPM_MM */ __RW_START__ = .; @@ -162,15 +162,15 @@ SECTIONS { * not mixed with normal data. This is required to set up the correct * memory attributes for the coherent data page tables. */ - coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { + .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { __COHERENT_RAM_START__ = .; /* * Bakery locks are stored in coherent memory. Each lock's data is * contiguous and fully allocated by the compiler. */ - *(bakery_lock) - *(tzfw_coherent_mem) + *(.bakery_lock) + *(.tzfw_coherent_mem) __COHERENT_RAM_END_UNALIGNED__ = .; diff --git a/bl32/sp_min/sp_min.ld.S b/bl32/sp_min/sp_min.ld.S index 59e164afa..1695e1e0a 100644 --- a/bl32/sp_min/sp_min.ld.S +++ b/bl32/sp_min/sp_min.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -62,7 +62,7 @@ SECTIONS { __RODATA_END__ = .; } >RAM #else /* SEPARATE_CODE_AND_RODATA */ - ro . : { + .ro . : { __RO_START__ = .; *entrypoint.o(.text*) @@ -115,15 +115,15 @@ SECTIONS { * not mixed with normal data. This is required to set up the correct * memory attributes for the coherent data page tables. */ - coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { + .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { __COHERENT_RAM_START__ = .; /* * Bakery locks are stored in coherent memory. Each lock's data is * contiguous and fully allocated by the compiler. */ - *(bakery_lock) - *(tzfw_coherent_mem) + *(.bakery_lock) + *(.tzfw_coherent_mem) __COHERENT_RAM_END_UNALIGNED__ = .; diff --git a/bl32/tsp/tsp.ld.S b/bl32/tsp/tsp.ld.S index 1e9cb8881..a6658dd7c 100644 --- a/bl32/tsp/tsp.ld.S +++ b/bl32/tsp/tsp.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -46,7 +46,7 @@ SECTIONS { __RODATA_END__ = .; } >RAM #else /* SEPARATE_CODE_AND_RODATA */ - ro . : { + .ro . : { __RO_START__ = .; *tsp_entrypoint.o(.text*) @@ -90,9 +90,9 @@ SECTIONS { * not mixed with normal data. This is required to set up the correct memory * attributes for the coherent data page tables. */ - coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { + .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { __COHERENT_RAM_START__ = .; - *(tzfw_coherent_mem) + *(.tzfw_coherent_mem) __COHERENT_RAM_END_UNALIGNED__ = .; /* diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst index 84bba18e6..36238a123 100644 --- a/docs/design/firmware-design.rst +++ b/docs/design/firmware-design.rst @@ -900,7 +900,7 @@ Registration A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying the name of the service, the range of OENs covered, the type of service and initialization and call handler functions. This macro instantiates a ``const struct rt_svc_desc`` for the service with these details (see ``runtime_svc.h``). -This structure is allocated in a special ELF section ``rt_svc_descs``, enabling +This structure is allocated in a special ELF section ``.rt_svc_descs``, enabling the framework to find all service descriptors included into BL31. The specific service for a SMC Function is selected based on the OEN and call @@ -2165,7 +2165,7 @@ To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structu has been redesigned. The changes utilise the characteristic of Lamport's Bakery algorithm mentioned earlier. The bakery_lock structure only allocates the memory for a single CPU. The macro ``DEFINE_BAKERY_LOCK`` allocates all the bakery locks -needed for a CPU into a section ``bakery_lock``. The linker allocates the memory +needed for a CPU into a section ``.bakery_lock``. The linker allocates the memory for other cores by using the total size allocated for the bakery_lock section and multiplying it with (PLATFORM_CORE_COUNT - 1). This enables software to perform software cache maintenance on the lock data structure without running @@ -2193,7 +2193,7 @@ with n bakery locks are: :: - bakery_lock section start + .bakery_lock section start |----------------| | `bakery_info_t`| <-- Lock_0 per-CPU field | Lock_0 | for CPU0 @@ -2230,7 +2230,7 @@ with n bakery locks are: Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1 -``bakery_lock`` section need to be fetched and appropriate cache operations need +``.bakery_lock`` section need to be fetched and appropriate cache operations need to be performed for each access. On Arm Platforms, bakery locks are used in psci (``psci_locks``) and power controller diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst index 80b72e52e..ec0a4689c 100644 --- a/docs/getting_started/porting-guide.rst +++ b/docs/getting_started/porting-guide.rst @@ -66,22 +66,22 @@ an identity mapping for all addresses. If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a block of identity mapped secure memory with Device-nGnRE attributes aligned to page boundary (4K) for each BL stage. All sections which allocate coherent -memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a -section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its +memory are grouped under ``.coherent_ram``. For ex: Bakery locks are placed in a +section identified by name ``.bakery_lock`` inside ``.coherent_ram`` so that its possible for the firmware to place variables in it using the following C code directive: :: - __section("bakery_lock") + __section(".bakery_lock") Or alternatively the following assembler code directive: :: - .section bakery_lock + .section .bakery_lock -The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are +The ``.coherent_ram`` section is a sum of all sections like ``.bakery_lock`` which are used to allocate any data structures that are accessed both when a CPU is executing with its MMU and caches enabled, and when it's running with its MMU and caches disabled. Examples are given below. @@ -2411,7 +2411,7 @@ bytes) aligned to the cache line boundary that should be allocated per-cpu to accommodate all the bakery locks. If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker -calculates the size of the ``bakery_lock`` input section, aligns it to the +calculates the size of the ``.bakery_lock`` input section, aligns it to the nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT`` and stores the result in a linker symbol. This constant prevents a platform from relying on the linker and provide a more efficient mechanism for @@ -3540,7 +3540,7 @@ amount of open resources per driver. -------------- -*Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.* .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf .. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html diff --git a/include/common/bl_common.ld.h b/include/common/bl_common.ld.h index 080e331ed..c9bed1ad9 100644 --- a/include/common/bl_common.ld.h +++ b/include/common/bl_common.ld.h @@ -24,7 +24,7 @@ #define CPU_OPS \ . = ALIGN(STRUCT_ALIGN); \ __CPU_OPS_START__ = .; \ - KEEP(*(cpu_ops)) \ + KEEP(*(.cpu_ops)) \ __CPU_OPS_END__ = .; #define PARSER_LIB_DESCS \ @@ -36,14 +36,14 @@ #define RT_SVC_DESCS \ . = ALIGN(STRUCT_ALIGN); \ __RT_SVC_DESCS_START__ = .; \ - KEEP(*(rt_svc_descs)) \ + KEEP(*(.rt_svc_descs)) \ __RT_SVC_DESCS_END__ = .; #if SPMC_AT_EL3 #define EL3_LP_DESCS \ . = ALIGN(STRUCT_ALIGN); \ __EL3_LP_DESCS_START__ = .; \ - KEEP(*(el3_lp_descs)) \ + KEEP(*(.el3_lp_descs)) \ __EL3_LP_DESCS_END__ = .; #else #define EL3_LP_DESCS @@ -52,7 +52,7 @@ #define PMF_SVC_DESCS \ . = ALIGN(STRUCT_ALIGN); \ __PMF_SVC_DESCS_START__ = .; \ - KEEP(*(pmf_svc_descs)) \ + KEEP(*(.pmf_svc_descs)) \ __PMF_SVC_DESCS_END__ = .; #define FCONF_POPULATOR \ @@ -81,7 +81,7 @@ #define BASE_XLAT_TABLE \ . = ALIGN(16); \ __BASE_XLAT_TABLE_START__ = .; \ - *(base_xlat_table) \ + *(.base_xlat_table) \ __BASE_XLAT_TABLE_END__ = .; #if PLAT_RO_XLAT_TABLES @@ -135,9 +135,9 @@ #if !(defined(IMAGE_BL31) && RECLAIM_INIT_CODE) #define STACK_SECTION \ - stacks (NOLOAD) : { \ + .stacks (NOLOAD) : { \ __STACKS_START__ = .; \ - *(tzfw_normal_stacks) \ + *(.tzfw_normal_stacks) \ __STACKS_END__ = .; \ } #endif @@ -170,7 +170,7 @@ . = ALIGN(CACHE_WRITEBACK_GRANULE); \ __BAKERY_LOCK_START__ = .; \ __PERCPU_BAKERY_LOCK_START__ = .; \ - *(bakery_lock) \ + *(.bakery_lock) \ . = ALIGN(CACHE_WRITEBACK_GRANULE); \ __PERCPU_BAKERY_LOCK_END__ = .; \ __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__); \ @@ -191,7 +191,7 @@ #define PMF_TIMESTAMP \ . = ALIGN(CACHE_WRITEBACK_GRANULE); \ __PMF_TIMESTAMP_START__ = .; \ - KEEP(*(pmf_timestamp_array)) \ + KEEP(*(.pmf_timestamp_array)) \ . = ALIGN(CACHE_WRITEBACK_GRANULE); \ __PMF_PERCPU_TIMESTAMP_END__ = .; \ __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); \ @@ -216,15 +216,15 @@ } /* - * The xlat_table section is for full, aligned page tables (4K). + * The .xlat_table section is for full, aligned page tables (4K). * Removing them from .bss avoids forcing 4K alignment on * the .bss section. The tables are initialized to zero by the translation * tables library. */ #define XLAT_TABLE_SECTION \ - xlat_table (NOLOAD) : { \ + .xlat_table (NOLOAD) : { \ __XLAT_TABLE_START__ = .; \ - *(xlat_table) \ + *(.xlat_table) \ __XLAT_TABLE_END__ = .; \ } diff --git a/include/common/runtime_svc.h b/include/common/runtime_svc.h index 472a32a1f..4793e2f3c 100644 --- a/include/common/runtime_svc.h +++ b/include/common/runtime_svc.h @@ -72,7 +72,7 @@ typedef struct rt_svc_desc { */ #define DECLARE_RT_SVC(_name, _start, _end, _type, _setup, _smch) \ static const rt_svc_desc_t __svc_desc_ ## _name \ - __section("rt_svc_descs") __used = { \ + __section(".rt_svc_descs") __used = { \ .start_oen = (_start), \ .end_oen = (_end), \ .call_type = (_type), \ diff --git a/include/lib/bakery_lock.h b/include/lib/bakery_lock.h index 1fece01af..2cf2b44eb 100644 --- a/include/lib/bakery_lock.h +++ b/include/lib/bakery_lock.h @@ -96,7 +96,7 @@ static inline void bakery_lock_init(bakery_lock_t *bakery) {} void bakery_lock_get(bakery_lock_t *bakery); void bakery_lock_release(bakery_lock_t *bakery); -#define DEFINE_BAKERY_LOCK(_name) bakery_lock_t _name __section("bakery_lock") +#define DEFINE_BAKERY_LOCK(_name) bakery_lock_t _name __section(".bakery_lock") #define DECLARE_BAKERY_LOCK(_name) extern bakery_lock_t _name diff --git a/include/lib/cpus/aarch32/cpu_macros.S b/include/lib/cpus/aarch32/cpu_macros.S index a5ae6a486..1f03f0992 100644 --- a/include/lib/cpus/aarch32/cpu_macros.S +++ b/include/lib/cpus/aarch32/cpu_macros.S @@ -129,7 +129,7 @@ */ .macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \ _power_down_ops:vararg - .section cpu_ops, "a" + .section .cpu_ops, "a" .align 2 .type cpu_ops_\_name, %object .word \_midr diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S index 92e65ae90..041be5153 100644 --- a/include/lib/cpus/aarch64/cpu_macros.S +++ b/include/lib/cpus/aarch64/cpu_macros.S @@ -157,7 +157,7 @@ */ .macro declare_cpu_ops_base _name:req, _midr:req, _resetfunc:req, \ _extra1:req, _extra2:req, _extra3:req, _e_handler:req, _power_down_ops:vararg - .section cpu_ops, "a" + .section .cpu_ops, "a" .align 3 .type cpu_ops_\_name, %object .quad \_midr diff --git a/include/lib/el3_runtime/pubsub.h b/include/lib/el3_runtime/pubsub.h index 64fe5ccb4..cbd8ecc05 100644 --- a/include/lib/el3_runtime/pubsub.h +++ b/include/lib/el3_runtime/pubsub.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,7 +12,7 @@ /* For the linker ... */ #define __pubsub_start_sym(event) __pubsub_##event##_start #define __pubsub_end_sym(event) __pubsub_##event##_end -#define __pubsub_section(event) __pubsub_##event +#define __pubsub_section(event) .__pubsub_##event /* * REGISTER_PUBSUB_EVENT has a different definition between linker and compiler @@ -54,7 +54,7 @@ #define __pubsub_end_sym(event) __pubsub_##event##_end #endif -#define __pubsub_section(event) __section("__pubsub_" #event) +#define __pubsub_section(event) __section(".__pubsub_" #event) /* * In compiler context, REGISTER_PUBSUB_EVENT declares the per-event symbols diff --git a/include/lib/pmf/pmf_helpers.h b/include/lib/pmf/pmf_helpers.h index b49c6da09..01cc179cf 100644 --- a/include/lib/pmf/pmf_helpers.h +++ b/include/lib/pmf/pmf_helpers.h @@ -154,7 +154,7 @@ typedef struct pmf_svc_desc { extern unsigned long long pmf_ts_mem_ ## _name[_total_id]; \ unsigned long long pmf_ts_mem_ ## _name[_total_id] \ __aligned(CACHE_WRITEBACK_GRANULE) \ - __section("pmf_timestamp_array") \ + __section(".pmf_timestamp_array") \ __used; /* @@ -225,7 +225,7 @@ typedef struct pmf_svc_desc { #define PMF_DEFINE_SERVICE_DESC(_name, _implid, _svcid, _totalid, \ _init, _getts_by_mpidr) \ static const pmf_svc_desc_t __pmf_desc_ ## _name \ - __section("pmf_svc_descs") __used = { \ + __section(".pmf_svc_descs") __used = { \ .h.type = PARAM_EP, \ .h.version = VERSION_1, \ .h.size = sizeof(pmf_svc_desc_t), \ diff --git a/include/lib/xlat_tables/xlat_tables_v2.h b/include/lib/xlat_tables/xlat_tables_v2.h index 69ad02764..4d16ced59 100644 --- a/include/lib/xlat_tables/xlat_tables_v2.h +++ b/include/lib/xlat_tables/xlat_tables_v2.h @@ -203,7 +203,7 @@ typedef struct xlat_ctx xlat_ctx_t; (_virt_addr_space_size), \ (_phy_addr_space_size), \ EL_REGIME_INVALID, \ - "xlat_table", "base_xlat_table") + ".xlat_table", ".base_xlat_table") /* * Same as REGISTER_XLAT_CONTEXT plus the additional parameters: diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index 7cd32b1f6..38793cd73 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -109,7 +109,7 @@ /* * Define a region within the TZC secured DRAM for use by EL3 runtime * firmware. This region is meant to be NOLOAD and will not be zero - * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be + * initialized. Data sections with the attribute `.arm_el3_tzc_dram` will be * placed here. 3MB region is reserved if RME is enabled, 2MB otherwise. */ #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00300000) /* 3MB */ diff --git a/include/plat/arm/common/arm_reclaim_init.ld.S b/include/plat/arm/common/arm_reclaim_init.ld.S index 788e9ff56..a77c96453 100644 --- a/include/plat/arm/common/arm_reclaim_init.ld.S +++ b/include/plat/arm/common/arm_reclaim_init.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -26,9 +26,9 @@ SECTIONS #define ABS ABSOLUTE #define STACK_SECTION \ - stacks (NOLOAD) : { \ + .stacks (NOLOAD) : { \ __STACKS_START__ = .; \ - *(tzfw_normal_stacks) \ + *(.tzfw_normal_stacks) \ __STACKS_END__ = .; \ /* Allow room for the init section where necessary. */ \ OFFSET = ABS(SIZEOF(.init) - (. - __STACKS_START__)); \ diff --git a/include/plat/arm/common/arm_tzc_dram.ld.S b/include/plat/arm/common/arm_tzc_dram.ld.S index 6dcea0b6e..c790bb927 100644 --- a/include/plat/arm/common/arm_tzc_dram.ld.S +++ b/include/plat/arm/common/arm_tzc_dram.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,9 +17,9 @@ SECTIONS . = ARM_EL3_TZC_DRAM1_BASE; ASSERT(. == ALIGN(PAGE_SIZE), "ARM_EL3_TZC_DRAM_BASE address is not aligned on a page boundary.") - el3_tzc_dram (NOLOAD) : ALIGN(PAGE_SIZE) { + .el3_tzc_dram (NOLOAD) : ALIGN(PAGE_SIZE) { __EL3_SEC_DRAM_START__ = .; - *(arm_el3_tzc_dram) + *(.arm_el3_tzc_dram) __EL3_SEC_DRAM_UNALIGNED_END__ = .; . = ALIGN(PAGE_SIZE); diff --git a/include/services/el3_spmc_logical_sp.h b/include/services/el3_spmc_logical_sp.h index 7ec9958d5..5ce33edbb 100644 --- a/include/services/el3_spmc_logical_sp.h +++ b/include/services/el3_spmc_logical_sp.h @@ -35,7 +35,7 @@ struct el3_lp_desc { #define DECLARE_LOGICAL_PARTITION(_name, _init, _sp_id, _uuid, _properties, \ _direct_req) \ static const struct el3_lp_desc __partition_desc_ ## _name \ - __section("el3_lp_descs") __used = { \ + __section(".el3_lp_descs") __used = { \ .debug_name = #_name, \ .init = (_init), \ .sp_id = (_sp_id), \ diff --git a/lib/pmf/pmf_main.c b/lib/pmf/pmf_main.c index 131a05578..ce2f0d9fd 100644 --- a/lib/pmf/pmf_main.c +++ b/lib/pmf/pmf_main.c @@ -17,7 +17,7 @@ /******************************************************************************* * The 'pmf_svc_descs' array holds the PMF service descriptors exported by - * services by placing them in the 'pmf_svc_descs' linker section. + * services by placing them in the '.pmf_svc_descs' linker section. * The 'pmf_svc_descs_indices' array holds the index of a descriptor in the * 'pmf_svc_descs' array. The TIF[15:10] bits in the time-stamp id are used * to get an index into the 'pmf_svc_descs_indices' array. This gives the diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c index 8d736cc14..f233be1f1 100644 --- a/lib/psci/psci_common.c +++ b/lib/psci/psci_common.c @@ -55,7 +55,7 @@ unsigned int psci_plat_core_count; ******************************************************************************/ non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS] #if USE_COHERENT_MEM -__section("tzfw_coherent_mem") +__section(".tzfw_coherent_mem") #endif ; diff --git a/lib/xlat_tables/aarch32/nonlpae_tables.c b/lib/xlat_tables/aarch32/nonlpae_tables.c index 7cd509d56..1e207a4dd 100644 --- a/lib/xlat_tables/aarch32/nonlpae_tables.c +++ b/lib/xlat_tables/aarch32/nonlpae_tables.c @@ -138,10 +138,10 @@ static unsigned long long xlat_max_pa; static uintptr_t xlat_max_va; static uint32_t mmu_l1_base[NUM_1MB_IN_4GB] - __aligned(MMU32B_L1_TABLE_ALIGN) __attribute__((section("xlat_table"))); + __aligned(MMU32B_L1_TABLE_ALIGN) __attribute__((section(".xlat_table"))); static uint32_t mmu_l2_base[MAX_XLAT_TABLES][NUM_4K_IN_1MB] - __aligned(MMU32B_L2_TABLE_ALIGN) __attribute__((section("xlat_table"))); + __aligned(MMU32B_L2_TABLE_ALIGN) __attribute__((section(".xlat_table"))); /* * Array of all memory regions stored in order of ascending base address. diff --git a/lib/xlat_tables/xlat_tables_common.c b/lib/xlat_tables/xlat_tables_common.c index 23fe3f0b4..71273cb97 100644 --- a/lib/xlat_tables/xlat_tables_common.c +++ b/lib/xlat_tables/xlat_tables_common.c @@ -39,7 +39,7 @@ #define MT_UNKNOWN ~0U static uint64_t xlat_tables[MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES] - __aligned(XLAT_TABLE_SIZE) __section("xlat_table"); + __aligned(XLAT_TABLE_SIZE) __section(".xlat_table"); static unsigned int next_xlat; static unsigned long long xlat_max_pa; diff --git a/plat/arm/board/arm_fpga/build_axf.ld.S b/plat/arm/board/arm_fpga/build_axf.ld.S index d8254e5b2..bd3d163d6 100644 --- a/plat/arm/board/arm_fpga/build_axf.ld.S +++ b/plat/arm/board/arm_fpga/build_axf.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, ARM Limited. All rights reserved. + * Copyright (c) 2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -46,7 +46,7 @@ SECTIONS KEEP(*(.kern_tramp)) } - /DISCARD/ : { *(stacks) } + /DISCARD/ : { *(.stacks) } /DISCARD/ : { *(.debug_*) } /DISCARD/ : { *(.note*) } /DISCARD/ : { *(.comment*) } diff --git a/plat/arm/board/fvp/fvp_el3_spmc.c b/plat/arm/board/fvp/fvp_el3_spmc.c index 2b347ed62..6b44f6345 100644 --- a/plat/arm/board/fvp/fvp_el3_spmc.c +++ b/plat/arm/board/fvp/fvp_el3_spmc.c @@ -18,7 +18,7 @@ #define PLAT_SPMC_SHMEM_DATASTORE_SIZE 512 * 1024 -__section("arm_el3_tzc_dram") static uint8_t +__section(".arm_el3_tzc_dram") static uint8_t plat_spmc_shmem_datastore[PLAT_SPMC_SHMEM_DATASTORE_SIZE]; int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size) diff --git a/plat/arm/common/aarch64/arm_helpers.S b/plat/arm/common/aarch64/arm_helpers.S index b47078173..ed85ea1dc 100644 --- a/plat/arm/common/aarch64/arm_helpers.S +++ b/plat/arm/common/aarch64/arm_helpers.S @@ -129,7 +129,7 @@ endfunc plat_set_my_stack * Single cpu stack in coherent memory. * ---------------------------------------------------- */ -declare_stack platform_coherent_stacks, tzfw_coherent_mem, \ +declare_stack platform_coherent_stacks, .tzfw_coherent_mem, \ PLATFORM_STACK_SIZE, 1, CACHE_WRITEBACK_GRANULE #endif /* defined(IMAGE_BL1) || defined(IMAGE_BL2) */ diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c index 469e22ade..1c95afb8c 100644 --- a/plat/arm/common/arm_gicv3.c +++ b/plat/arm/common/arm_gicv3.c @@ -48,8 +48,8 @@ static const interrupt_prop_t arm_interrupt_props[] = { * data in the designated EL3 Secure carve-out memory. The `used` attribute * is used to prevent the compiler from removing the gicv3 contexts. */ -static gicv3_redist_ctx_t rdist_ctx __section("arm_el3_tzc_dram") __used; -static gicv3_dist_ctx_t dist_ctx __section("arm_el3_tzc_dram") __used; +static gicv3_redist_ctx_t rdist_ctx __section(".arm_el3_tzc_dram") __used; +static gicv3_dist_ctx_t dist_ctx __section(".arm_el3_tzc_dram") __used; /* Define accessor function to get reference to the GICv3 context */ DEFINE_LOAD_SYM_ADDR(rdist_ctx) diff --git a/plat/common/aarch32/platform_mp_stack.S b/plat/common/aarch32/platform_mp_stack.S index 6c3d08de3..314e87a3a 100644 --- a/plat/common/aarch32/platform_mp_stack.S +++ b/plat/common/aarch32/platform_mp_stack.S @@ -43,5 +43,5 @@ endfunc plat_set_my_stack * stack of PLATFORM_STACK_SIZE bytes. * ----------------------------------------------------- */ -declare_stack platform_normal_stacks, tzfw_normal_stacks, \ +declare_stack platform_normal_stacks, .tzfw_normal_stacks, \ PLATFORM_STACK_SIZE, PLATFORM_CORE_COUNT diff --git a/plat/common/aarch32/platform_up_stack.S b/plat/common/aarch32/platform_up_stack.S index 836c13ae6..69e112f27 100644 --- a/plat/common/aarch32/platform_up_stack.S +++ b/plat/common/aarch32/platform_up_stack.S @@ -43,5 +43,5 @@ endfunc plat_set_my_stack * stack of PLATFORM_STACK_SIZE bytes. * ----------------------------------------------------- */ -declare_stack platform_normal_stacks, tzfw_normal_stacks, \ +declare_stack platform_normal_stacks, .tzfw_normal_stacks, \ PLATFORM_STACK_SIZE, 1, CACHE_WRITEBACK_GRANULE diff --git a/plat/common/aarch64/platform_mp_stack.S b/plat/common/aarch64/platform_mp_stack.S index c0668ea78..fa1ca22d5 100644 --- a/plat/common/aarch64/platform_mp_stack.S +++ b/plat/common/aarch64/platform_mp_stack.S @@ -56,6 +56,6 @@ endfunc plat_set_my_stack * stack of PLATFORM_STACK_SIZE bytes. * ----------------------------------------------------- */ -declare_stack platform_normal_stacks, tzfw_normal_stacks, \ +declare_stack platform_normal_stacks, .tzfw_normal_stacks, \ PLATFORM_STACK_SIZE, PLATFORM_CORE_COUNT, \ CACHE_WRITEBACK_GRANULE diff --git a/plat/common/aarch64/platform_up_stack.S b/plat/common/aarch64/platform_up_stack.S index c6e5e2d74..2c8721918 100644 --- a/plat/common/aarch64/platform_up_stack.S +++ b/plat/common/aarch64/platform_up_stack.S @@ -46,5 +46,5 @@ endfunc plat_set_my_stack * are allocated * ----------------------------------------------------- */ -declare_stack platform_normal_stacks, tzfw_normal_stacks, \ +declare_stack platform_normal_stacks, .tzfw_normal_stacks, \ PLATFORM_STACK_SIZE, 1, CACHE_WRITEBACK_GRANULE diff --git a/plat/hisilicon/hikey960/hikey960_bl31_setup.c b/plat/hisilicon/hikey960/hikey960_bl31_setup.c index 0debe1ee6..50751ee38 100644 --- a/plat/hisilicon/hikey960/hikey960_bl31_setup.c +++ b/plat/hisilicon/hikey960/hikey960_bl31_setup.c @@ -183,7 +183,7 @@ static void hikey960_iomcu_dma_init(void) #define SPMC_SHARED_MEMORY_OBJ_SIZE (512 * 1024) -__section("ram2_region") uint8_t plat_spmc_shmem_datastore[SPMC_SHARED_MEMORY_OBJ_SIZE]; +__section(".ram2_region") uint8_t plat_spmc_shmem_datastore[SPMC_SHARED_MEMORY_OBJ_SIZE]; int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size) { diff --git a/plat/hisilicon/hikey960/include/plat.ld.S b/plat/hisilicon/hikey960/include/plat.ld.S index 0cc25cdac..f8bd37611 100644 --- a/plat/hisilicon/hikey960/include/plat.ld.S +++ b/plat/hisilicon/hikey960/include/plat.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,8 +14,8 @@ MEMORY { SECTIONS { - ram2_region (NOLOAD) : { - *(ram2_region) + .ram2_region (NOLOAD) : { + *(.ram2_region) }>RAM2 } diff --git a/plat/marvell/armada/a8k/common/ble/ble.ld.S b/plat/marvell/armada/a8k/common/ble/ble.ld.S index d7a05928c..446849b36 100644 --- a/plat/marvell/armada/a8k/common/ble/ble.ld.S +++ b/plat/marvell/armada/a8k/common/ble/ble.ld.S @@ -19,7 +19,7 @@ SECTIONS { . = BLE_BASE; - ro . : { + .ro . : { __RO_START__ = .; *ble_main.o(.entry*) *(.text*) @@ -40,9 +40,9 @@ SECTIONS __DATA_END__ = .; } >RAM - stacks . (NOLOAD) : { + .stacks . (NOLOAD) : { __STACKS_START__ = .; - *(tzfw_normal_stacks) + *(.tzfw_normal_stacks) __STACKS_END__ = .; } >RAM diff --git a/plat/marvell/armada/common/marvell_gicv3.c b/plat/marvell/armada/common/marvell_gicv3.c index 0bd554570..5419506e7 100644 --- a/plat/marvell/armada/common/marvell_gicv3.c +++ b/plat/marvell/armada/common/marvell_gicv3.c @@ -38,8 +38,8 @@ static const interrupt_prop_t marvell_interrupt_props[] = { * We save and restore the GICv3 context on system suspend. Allocate the * data in the designated EL3 Secure carve-out memory */ -static gicv3_redist_ctx_t rdist_ctx __section("arm_el3_tzc_dram"); -static gicv3_dist_ctx_t dist_ctx __section("arm_el3_tzc_dram"); +static gicv3_redist_ctx_t rdist_ctx __section(".arm_el3_tzc_dram"); +static gicv3_dist_ctx_t dist_ctx __section(".arm_el3_tzc_dram"); /* * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register diff --git a/plat/mediatek/common/mtk_smc_handlers.c b/plat/mediatek/common/mtk_smc_handlers.c index 92b3873c3..a8a5a482e 100644 --- a/plat/mediatek/common/mtk_smc_handlers.c +++ b/plat/mediatek/common/mtk_smc_handlers.c @@ -72,7 +72,7 @@ } #define SMC_ID_EXPAND_AS_DESCRIPTOR_INDEX(_smc_id, _smc_num) \ - short _smc_id##_descriptor_index __section("mtk_plat_ro") = -1; + short _smc_id##_descriptor_index __section(".mtk_plat_ro") = -1; MTK_SIP_SMC_FROM_BL33_TABLE(SMC_ID_EXPAND_AS_DESCRIPTOR_INDEX); MTK_SIP_SMC_FROM_NS_EL1_TABLE(SMC_ID_EXPAND_AS_DESCRIPTOR_INDEX); diff --git a/plat/mediatek/include/plat.ld.rodata.inc b/plat/mediatek/include/plat.ld.rodata.inc index 06ad49109..e76647261 100644 --- a/plat/mediatek/include/plat.ld.rodata.inc +++ b/plat/mediatek/include/plat.ld.rodata.inc @@ -25,6 +25,6 @@ __MTK_SMC_POOL_END_UNALIGNED__ = .; . = ALIGN(8); #include <vendor_pubsub_events.h> - *(mtk_plat_ro) + *(.mtk_plat_ro) #endif /* PLAT_LD_RODATA_INC */ diff --git a/plat/mediatek/mt8173/drivers/spm/spm.c b/plat/mediatek/mt8173/drivers/spm/spm.c index 1caab3bdf..8980e075e 100644 --- a/plat/mediatek/mt8173/drivers/spm/spm.c +++ b/plat/mediatek/mt8173/drivers/spm/spm.c @@ -29,9 +29,9 @@ DEFINE_BAKERY_LOCK(spm_lock); -static int spm_hotplug_ready __section("tzfw_coherent_mem"); -static int spm_mcdi_ready __section("tzfw_coherent_mem"); -static int spm_suspend_ready __section("tzfw_coherent_mem"); +static int spm_hotplug_ready __section(".tzfw_coherent_mem"); +static int spm_mcdi_ready __section(".tzfw_coherent_mem"); +static int spm_suspend_ready __section(".tzfw_coherent_mem"); void spm_lock_init(void) { diff --git a/plat/mediatek/mt8186/drivers/mcdi/mt_mcdi.c b/plat/mediatek/mt8186/drivers/mcdi/mt_mcdi.c index 010361208..efcf87f70 100644 --- a/plat/mediatek/mt8186/drivers/mcdi/mt_mcdi.c +++ b/plat/mediatek/mt8186/drivers/mcdi/mt_mcdi.c @@ -62,7 +62,7 @@ #define MCDI_INIT_2 U(2) #define MCDI_INIT_DONE U(3) -static int mcdi_init_status __section("tzfw_coherent_mem"); +static int mcdi_init_status __section(".tzfw_coherent_mem"); static inline uint32_t mcdi_mbox_read(uint32_t id) { diff --git a/plat/mediatek/mt8192/drivers/mcdi/mt_mcdi.c b/plat/mediatek/mt8192/drivers/mcdi/mt_mcdi.c index 1635b67b3..765c7b21c 100644 --- a/plat/mediatek/mt8192/drivers/mcdi/mt_mcdi.c +++ b/plat/mediatek/mt8192/drivers/mcdi/mt_mcdi.c @@ -63,7 +63,7 @@ #define MCDI_INIT_2 2 #define MCDI_INIT_DONE 3 -static int mcdi_init_status __section("tzfw_coherent_mem"); +static int mcdi_init_status __section(".tzfw_coherent_mem"); static inline uint32_t mcdi_mbox_read(uint32_t id) { diff --git a/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.c b/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.c index c14e83b64..f7dfec3d1 100644 --- a/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.c +++ b/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.c @@ -63,7 +63,7 @@ #define MCDI_INIT_2 2 #define MCDI_INIT_DONE 3 -static int mcdi_init_status __section("tzfw_coherent_mem"); +static int mcdi_init_status __section(".tzfw_coherent_mem"); static inline uint32_t mcdi_mbox_read(uint32_t id) { diff --git a/plat/nvidia/tegra/platform.mk b/plat/nvidia/tegra/platform.mk index 6ed1cdf0b..236556499 100644 --- a/plat/nvidia/tegra/platform.mk +++ b/plat/nvidia/tegra/platform.mk @@ -90,8 +90,8 @@ ifneq ($(findstring armlink,$(notdir $(LD))),) # o resolve undefined symbols to el3_panic # o include only required sections TF_LDFLAGS += --diag_suppress=L6314,L6332 --no_scanlib --callgraph -TF_LDFLAGS += --keep="*(__pubsub*)" --keep="*(rt_svc_descs*)" --keep="*(*cpu_ops)" +TF_LDFLAGS += --keep="*(.__pubsub*)" --keep="*(.rt_svc_descs*)" --keep="*(.cpu_ops)" ifeq (${ENABLE_PMF},1) -TF_LDFLAGS += --keep="*(*pmf_svc_descs*)" +TF_LDFLAGS += --keep="*(.pmf_svc_descs*)" endif endif diff --git a/plat/nvidia/tegra/scat/bl31.scat b/plat/nvidia/tegra/scat/bl31.scat index 2d6d2b3d2..fdd6e3352 100644 --- a/plat/nvidia/tegra/scat/bl31.scat +++ b/plat/nvidia/tegra/scat/bl31.scat @@ -48,14 +48,14 @@ LR_RO_DATA +0 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ __RT_SVC_DESCS__ AlignExpr(ImageLimit(__RODATA__), 8) FIXED { - *(rt_svc_descs) + *(.rt_svc_descs) } #if ENABLE_PMF /* Ensure 8-byte alignment for descriptors and ensure inclusion */ __PMF_SVC_DESCS__ AlignExpr(ImageLimit(__RT_SVC_DESCS__), 8) FIXED { - *(pmf_svc_descs) + *(.pmf_svc_descs) } #endif /* ENABLE_PMF */ @@ -65,7 +65,7 @@ LR_RO_DATA +0 */ __CPU_OPS__ AlignExpr(+0, 8) FIXED { - *(cpu_ops) + *(.cpu_ops) } /* @@ -150,7 +150,7 @@ LR_STACKS +0 { __STACKS__ AlignExpr(+0, 64) FIXED { - *(tzfw_normal_stacks) + *(.tzfw_normal_stacks) } } @@ -180,7 +180,7 @@ LR_BSS +0 */ __BAKERY_LOCKS__ AlignExpr(ImageLimit(__BSS__), CACHE_WRITEBACK_GRANULE) FIXED { - *(bakery_lock) + *(.bakery_lock) } __BAKERY_LOCKS_EPILOGUE__ AlignExpr(ImageLimit(__BAKERY_LOCKS__), CACHE_WRITEBACK_GRANULE) FIXED EMPTY 0 @@ -229,9 +229,9 @@ LR_BSS +0 LR_XLAT_TABLE +0 { - xlat_table +0 FIXED + .xlat_table +0 FIXED { - *(xlat_table) + *(.xlat_table) } } @@ -251,8 +251,8 @@ LR_COHERENT_RAM +0 * * Each lock's data is contiguous and fully allocated by the compiler */ - *(bakery_lock) - *(tzfw_coherent_mem) + *(.bakery_lock) + *(.tzfw_coherent_mem) } __COHERENT_RAM_EPILOGUE_UNALIGNED__ +0 FIXED EMPTY 0 diff --git a/plat/qemu/qemu_sbsa/include/platform_def.h b/plat/qemu/qemu_sbsa/include/platform_def.h index d971ebe9e..85fbb4dd5 100644 --- a/plat/qemu/qemu_sbsa/include/platform_def.h +++ b/plat/qemu/qemu_sbsa/include/platform_def.h @@ -364,8 +364,8 @@ * Name of the section to put the translation tables used by the S-EL1/S-EL0 * context of a Secure Partition. */ -#define PLAT_SP_IMAGE_XLAT_SECTION_NAME "qemu_sp_xlat_table" -#define PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME "qemu_sp_xlat_table" +#define PLAT_SP_IMAGE_XLAT_SECTION_NAME ".qemu_sp_xlat_table" +#define PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME ".qemu_sp_xlat_table" /* Cookies passed to the Secure Partition at boot. Not used by QEMU platforms.*/ #define PLAT_SPM_COOKIE_0 ULL(0) diff --git a/plat/renesas/common/aarch64/platform_common.c b/plat/renesas/common/aarch64/platform_common.c index b0a88cb6b..17ccb2820 100644 --- a/plat/renesas/common/aarch64/platform_common.c +++ b/plat/renesas/common/aarch64/platform_common.c @@ -28,7 +28,7 @@ extern int32_t rcar_get_certificate(const int32_t name, uint32_t *cert); #endif const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN] - __attribute__ ((__section__("ro"))) = VERSION_OF_RENESAS; + __attribute__ ((__section__(".ro"))) = VERSION_OF_RENESAS; #define MAP_SHARED_RAM MAP_REGION_FLAT(RCAR_SHARED_MEM_BASE, \ RCAR_SHARED_MEM_SIZE, \ diff --git a/plat/rockchip/common/aarch32/plat_helpers.S b/plat/rockchip/common/aarch32/plat_helpers.S index 475c2972f..9f49cbd26 100644 --- a/plat/rockchip/common/aarch32/plat_helpers.S +++ b/plat/rockchip/common/aarch32/plat_helpers.S @@ -151,7 +151,7 @@ endfunc platform_cpu_warmboot * Per-CPU Secure entry point - resume or power up * -------------------------------------------------------------------- */ - .section tzfw_coherent_mem, "a" + .section .tzfw_coherent_mem, "a" .align 3 cpuson_entry_point: .rept PLATFORM_CORE_COUNT diff --git a/plat/rockchip/common/aarch64/plat_helpers.S b/plat/rockchip/common/aarch64/plat_helpers.S index 4af052b57..c4c0dec3c 100644 --- a/plat/rockchip/common/aarch64/plat_helpers.S +++ b/plat/rockchip/common/aarch64/plat_helpers.S @@ -150,7 +150,7 @@ endfunc platform_cpu_warmboot * Per-CPU Secure entry point - resume or power up * -------------------------------------------------------------------- */ - .section tzfw_coherent_mem, "a" + .section .tzfw_coherent_mem, "a" .align 3 cpuson_entry_point: .rept PLATFORM_CORE_COUNT diff --git a/plat/rockchip/px30/drivers/pmu/pmu.c b/plat/rockchip/px30/drivers/pmu/pmu.c index 5f4e64f7b..8770b2e11 100644 --- a/plat/rockchip/px30/drivers/pmu/pmu.c +++ b/plat/rockchip/px30/drivers/pmu/pmu.c @@ -45,7 +45,7 @@ static struct psram_data_t *psram_boot_cfg = static uint32_t cores_pd_cfg_info[PLATFORM_CORE_COUNT] #if USE_COHERENT_MEM -__attribute__ ((section("tzfw_coherent_mem"))) +__attribute__ ((section(".tzfw_coherent_mem"))) #endif ; @@ -101,7 +101,7 @@ struct px30_sleep_ddr_data { static struct px30_sleep_ddr_data ddr_data #if USE_COHERENT_MEM -__attribute__ ((section("tzfw_coherent_mem"))) +__attribute__ ((section(".tzfw_coherent_mem"))) #endif ; diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c index 3084c4f2f..7bdefcce8 100644 --- a/plat/rockchip/rk3399/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c @@ -64,7 +64,7 @@ static gicv3_redist_ctx_t rdist_ctx; static uint32_t core_pm_cfg_info[PLATFORM_CORE_COUNT] #if USE_COHERENT_MEM -__attribute__ ((section("tzfw_coherent_mem"))) +__attribute__ ((section(".tzfw_coherent_mem"))) #endif ;/* coheront */ diff --git a/plat/socionext/synquacer/include/plat.ld.S b/plat/socionext/synquacer/include/plat.ld.S index af7a172db..d02afa766 100644 --- a/plat/socionext/synquacer/include/plat.ld.S +++ b/plat/socionext/synquacer/include/plat.ld.S @@ -23,8 +23,8 @@ SECTIONS * not support inner shareable WBWA mappings so it is mapped normal * non-cacheable) */ - sp_xlat_table (NOLOAD) : ALIGN(PAGE_SIZE) { - *(sp_xlat_table) + .sp_xlat_table (NOLOAD) : ALIGN(PAGE_SIZE) { + *(.sp_xlat_table) } >SP_DRAM } diff --git a/plat/socionext/synquacer/include/platform_def.h b/plat/socionext/synquacer/include/platform_def.h index d6bfe42e1..acc74e246 100644 --- a/plat/socionext/synquacer/include/platform_def.h +++ b/plat/socionext/synquacer/include/platform_def.h @@ -180,8 +180,8 @@ #define PLAT_SP_IMAGE_MMAP_REGIONS 30 #define PLAT_SP_IMAGE_MAX_XLAT_TABLES 20 -#define PLAT_SP_IMAGE_XLAT_SECTION_NAME "sp_xlat_table" -#define PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME "sp_xlat_table" +#define PLAT_SP_IMAGE_XLAT_SECTION_NAME ".sp_xlat_table" +#define PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME ".sp_xlat_table" #define PLAT_SQ_UART1_BASE PLAT_SQ_BOOT_UART_BASE #define PLAT_SQ_UART1_SIZE ULL(0x1000) diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c b/plat/ti/k3/common/drivers/ti_sci/ti_sci.c index 569e60c16..ade10a6fe 100644 --- a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c +++ b/plat/ti/k3/common/drivers/ti_sci/ti_sci.c @@ -21,7 +21,7 @@ #include "ti_sci.h" #if USE_COHERENT_MEM -__section("tzfw_coherent_mem") +__section(".tzfw_coherent_mem") #endif static uint8_t message_sequence; diff --git a/plat/xilinx/versal/versal_gicv3.c b/plat/xilinx/versal/versal_gicv3.c index d41090699..0959c8e94 100644 --- a/plat/xilinx/versal/versal_gicv3.c +++ b/plat/xilinx/versal/versal_gicv3.c @@ -36,8 +36,8 @@ static const interrupt_prop_t versal_interrupt_props[] = { * We save and restore the GICv3 context on system suspend. Allocate the * data in the designated EL3 Secure carve-out memory. */ -static gicv3_redist_ctx_t rdist_ctx __section("versal_el3_tzc_dram"); -static gicv3_dist_ctx_t dist_ctx __section("versal_el3_tzc_dram"); +static gicv3_redist_ctx_t rdist_ctx __section(".versal_el3_tzc_dram"); +static gicv3_dist_ctx_t dist_ctx __section(".versal_el3_tzc_dram"); /* * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register diff --git a/plat/xilinx/versal_net/versal_net_gicv3.c b/plat/xilinx/versal_net/versal_net_gicv3.c index 1d45a5887..138d2c2a6 100644 --- a/plat/xilinx/versal_net/versal_net_gicv3.c +++ b/plat/xilinx/versal_net/versal_net_gicv3.c @@ -39,8 +39,8 @@ static const interrupt_prop_t versal_net_interrupt_props[] = { * We save and restore the GICv3 context on system suspend. Allocate the * data in the designated EL3 Secure carve-out memory. */ -static gicv3_redist_ctx_t rdist_ctx __section("versal_net_el3_tzc_dram"); -static gicv3_dist_ctx_t dist_ctx __section("versal_net_el3_tzc_dram"); +static gicv3_redist_ctx_t rdist_ctx __section(".versal_net_el3_tzc_dram"); +static gicv3_dist_ctx_t dist_ctx __section(".versal_net_el3_tzc_dram"); /* * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register diff --git a/services/std_svc/spm/spm_mm/spm_mm_xlat.c b/services/std_svc/spm/spm_mm/spm_mm_xlat.c index 6261016f7..b1ca55ae3 100644 --- a/services/std_svc/spm/spm_mm/spm_mm_xlat.c +++ b/services/std_svc/spm/spm_mm/spm_mm_xlat.c @@ -19,7 +19,7 @@ /* Place translation tables by default along with the ones used by BL31. */ #ifndef PLAT_SP_IMAGE_XLAT_SECTION_NAME -#define PLAT_SP_IMAGE_XLAT_SECTION_NAME "xlat_table" +#define PLAT_SP_IMAGE_XLAT_SECTION_NAME ".xlat_table" #endif #ifndef PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME #define PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME ".bss" |