diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/arch/aarch64/arch.h | 10 | ||||
| -rw-r--r-- | include/arch/aarch64/arch_features.h | 18 | ||||
| -rw-r--r-- | include/arch/aarch64/arch_helpers.h | 4 | ||||
| -rw-r--r-- | include/lib/el3_runtime/aarch64/context.h | 4 |
4 files changed, 35 insertions, 1 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 89f4b40bd..9e061bfb4 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -371,6 +371,9 @@ #define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf) /* ID_AA64PFR1_EL1 definitions */ +#define ID_AA64PFR1_EL1_GCS_SHIFT U(44) +#define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf) + #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) @@ -527,6 +530,7 @@ #define SCR_PIEN_BIT (UL(1) << 45) #define SCR_TCR2EN_BIT (UL(1) << 43) #define SCR_TRNDR_BIT (UL(1) << 40) +#define SCR_GCSEn_BIT (UL(1) << 39) #define SCR_HXEn_BIT (UL(1) << 38) #define SCR_ENTP2_SHIFT U(41) #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) @@ -1351,6 +1355,12 @@ #define S2PIR_EL2 S3_4_C10_C2_5 /******************************************************************************* + * FEAT_GCS - Guarded Control Stack Registers + ******************************************************************************/ +#define GCSCR_EL2 S3_4_C2_C5_0 +#define GCSPR_EL2 S3_4_C2_C5_1 + +/******************************************************************************* * Definitions for DynamicIQ Shared Unit registers ******************************************************************************/ #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h index 840b117a0..16f4fb996 100644 --- a/include/arch/aarch64/arch_features.h +++ b/include/arch/aarch64/arch_features.h @@ -316,6 +316,24 @@ static inline bool is_feat_sxpie_supported(void) return is_feat_s1pie_supported() || is_feat_s2pie_supported(); } +static unsigned int read_feat_gcs_id_field(void) +{ + return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_GCS); +} + +static inline bool is_feat_gcs_supported(void) +{ + if (ENABLE_FEAT_GCS == FEAT_STATE_DISABLED) { + return false; + } + + if (ENABLE_FEAT_GCS == FEAT_STATE_ALWAYS) { + return true; + } + + return read_feat_gcs_id_field() != 0U; +} + /******************************************************************************* * Functions to identify the presence of the Activity Monitors Extension ******************************************************************************/ diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h index f877f5bc8..1b4bc1113 100644 --- a/include/arch/aarch64/arch_helpers.h +++ b/include/arch/aarch64/arch_helpers.h @@ -613,6 +613,10 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(s2pir_el2, S2PIR_EL2) /* FEAT_SxPOE Registers */ DEFINE_RENAME_SYSREG_RW_FUNCS(por_el2, POR_EL2) +/* FEAT_GCS Registers */ +DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el2, GCSCR_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el2, GCSPR_EL2) + /* DynamIQ Shared Unit power management */ DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1) diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h index a8e6d8ad2..dd2b83681 100644 --- a/include/lib/el3_runtime/aarch64/context.h +++ b/include/lib/el3_runtime/aarch64/context.h @@ -234,9 +234,11 @@ #define CTX_PIRE0_EL2 U(0x1e8) #define CTX_PIR_EL2 U(0x1f0) #define CTX_S2PIR_EL2 U(0x1f8) +#define CTX_GCSCR_EL2 U(0x200) +#define CTX_GCSPR_EL2 U(0x208) /* Align to the next 16 byte boundary */ -#define CTX_EL2_SYSREGS_END U(0x200) +#define CTX_EL2_SYSREGS_END U(0x210) #endif /* CTX_INCLUDE_EL2_REGS */ |