diff options
Diffstat (limited to 'lib')
-rw-r--r-- | lib/el3_runtime/aarch64/context_mgmt.c | 68 | ||||
-rw-r--r-- | lib/extensions/sme/sme.c | 14 | ||||
-rw-r--r-- | lib/extensions/sve/sve.c | 19 |
3 files changed, 36 insertions, 65 deletions
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 7fbbd8171..42166eb99 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -492,11 +492,10 @@ static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) /* Enable SME, SVE, and FPU/SIMD for non-secure world. */ if (is_feat_sme_supported()) { sme_enable(ctx); + } else if (is_feat_sve_supported()) { + /* Enable SVE and FPU/SIMD for non-secure world. */ + sve_enable(ctx); } -#if ENABLE_SVE_FOR_NS - /* Enable SVE and FPU/SIMD for non-secure world. */ - sve_enable(ctx); -#endif if (is_feat_mpam_supported()) { mpam_enable(el2_unused); @@ -526,35 +525,38 @@ static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) static void manage_extensions_secure(cpu_context_t *ctx) { #if IMAGE_BL31 - #if ENABLE_SME_FOR_NS - #if ENABLE_SME_FOR_SWD - /* - * Enable SME, SVE, FPU/SIMD in secure context, secure manager must - * ensure SME, SVE, and FPU/SIMD context properly managed. - */ - sme_enable(ctx); - #else /* ENABLE_SME_FOR_SWD */ - /* - * Disable SME, SVE, FPU/SIMD in secure context so non-secure world can - * safely use the associated registers. - */ - sme_disable(ctx); - #endif /* ENABLE_SME_FOR_SWD */ - #elif ENABLE_SVE_FOR_NS - #if ENABLE_SVE_FOR_SWD - /* - * Enable SVE and FPU in secure context, secure manager must ensure that - * the SVE and FPU register contexts are properly managed. - */ - sve_enable(ctx); - #else /* ENABLE_SVE_FOR_SWD */ - /* - * Disable SVE and FPU in secure context so non-secure world can safely - * use them. - */ - sve_disable(ctx); - #endif /* ENABLE_SVE_FOR_SWD */ - #endif /* ENABLE_SVE_FOR_NS */ + + if (is_feat_sme_supported()) { + if (ENABLE_SME_FOR_SWD) { + /* + * Enable SME, SVE, FPU/SIMD in secure context, secure manager + * must ensure SME, SVE, and FPU/SIMD context properly managed. + */ + sme_enable(ctx); + } else { + /* + * Disable SME, SVE, FPU/SIMD in secure context so non-secure + * world can safely use the associated registers. + */ + sme_disable(ctx); + } + } else if (is_feat_sve_supported()) { + if (ENABLE_SVE_FOR_SWD) { + /* + * Enable SVE and FPU in secure context, secure manager must + * ensure that the SVE and FPU register contexts are properly + * managed. + */ + sve_enable(ctx); + } else { + /* + * Disable SVE and FPU in secure context so non-secure world + * can safely use them. + */ + sve_disable(ctx); + } + } + #endif /* IMAGE_BL31 */ } diff --git a/lib/extensions/sme/sme.c b/lib/extensions/sme/sme.c index 1846e003a..29034fdc4 100644 --- a/lib/extensions/sme/sme.c +++ b/lib/extensions/sme/sme.c @@ -20,13 +20,6 @@ void sme_enable(cpu_context_t *context) u_register_t cptr_el3; el3_state_t *state; - /* Make sure SME is implemented in hardware before continuing. */ - if (!is_feat_sme_supported()) { - /* Perhaps the hardware supports SVE only */ - sve_enable(context); - return; - } - /* Get the context state. */ state = get_el3state_ctx(context); @@ -70,13 +63,6 @@ void sme_disable(cpu_context_t *context) u_register_t reg; el3_state_t *state; - /* Make sure SME is implemented in hardware before continuing. */ - if (!is_feat_sme_supported()) { - /* Perhaps the hardware supports SVE only */ - sve_disable(context); - return; - } - /* Get the context state. */ state = get_el3state_ctx(context); diff --git a/lib/extensions/sve/sve.c b/lib/extensions/sve/sve.c index f7dcc767a..f551ca7e6 100644 --- a/lib/extensions/sve/sve.c +++ b/lib/extensions/sve/sve.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,22 +22,10 @@ CASSERT((SVE_VECTOR_LEN % 128) == 0, assert_sve_vl_granule); */ #define CONVERT_SVE_LENGTH(x) (((x / 128) - 1)) -static bool sve_supported(void) -{ - uint64_t features; - - features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT; - return (features & ID_AA64PFR0_SVE_MASK) == 1U; -} - void sve_enable(cpu_context_t *context) { u_register_t cptr_el3; - if (!sve_supported()) { - return; - } - cptr_el3 = read_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3); /* Enable access to SVE functionality for all ELs. */ @@ -54,11 +42,6 @@ void sve_disable(cpu_context_t *context) u_register_t reg; el3_state_t *state; - /* Make sure SME is implemented in hardware before continuing. */ - if (!sve_supported()) { - return; - } - /* Get the context state. */ state = get_el3state_ctx(context); |