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* Merge changes from topic "mp/feat_ras" into integrationManish Pandey2023-05-091-8/+16
|\ | | | | | | | | | | * changes: refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED refactor(ras): replace RAS_EXTENSION with FEAT_RAS
| * refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKEDAndre Przywara2023-05-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_RAS to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (FEAT_RAS=2), by splitting is_armv8_2_feat_ras_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access RAS related registers. Also move the context saving code from assembly to C, and use the new is_feat_ras_supported() function to guard its execution. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I30498f72fd80b136850856244687400456a03d0e Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
| * refactor(ras): replace RAS_EXTENSION with FEAT_RASManish Pandey2023-05-091-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current usage of RAS_EXTENSION in TF-A codebase is to cater for two things in TF-A : 1. Pull in necessary framework and platform hooks for Firmware first handling(FFH) of RAS errors. 2. Manage the FEAT_RAS extension when switching the worlds. FFH means that all the EAs from NS are trapped in EL3 first and signaled to NS world later after the first handling is done in firmware. There is an alternate way of handling RAS errors viz Kernel First handling(KFH). Tying FEAT_RAS to RAS_EXTENSION build flag was not correct as the feature is needed for proper handling KFH in as well. This patch breaks down the RAS_EXTENSION flag into a flag to denote the CPU architecture `ENABLE_FEAT_RAS` which is used in context management during world switch and another flag `RAS_FFH_SUPPORT` to pull in required framework and platform hooks for FFH. Proper support for KFH will be added in future patches. BREAKING CHANGE: The previous RAS_EXTENSION is now deprecated. The equivalent functionality can be achieved by the following 2 options: - ENABLE_FEAT_RAS - RAS_FFH_SUPPORT Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I1abb9ab6622b8f1b15712b12f17612804d48a6ec
* | Merge changes from topic "srm/Errata_ABI_El3" into integrationMadhukar Pappireddy2023-05-091-0/+4
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | * changes: docs(errata_abi): document the errata abi changes feat(fvp): enable errata management interface fix(cpus): workaround platforms non-arm interconnect refactor(errata_abi): factor in non-arm interconnect feat(errata_abi): errata management firmware interface
| * | refactor(errata_abi): factor in non-arm interconnectSona Mathew2023-05-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Workaround to help enable the kernel to query errata status using the errata abi feature for platforms with a non-arm interconnect. Change-Id: I47b03eaee5a0a763056ae71883fa30dfacb9b3f7 Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
| * | feat(errata_abi): errata management firmware interfaceSona Mathew2023-05-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the errata management firmware interface for lower ELs to discover details about CPU erratum. Based on the CPU erratum identifier the interface enables the OS to find the mitigation of an erratum in EL3. The ABI can only be present in a system that is compliant with SMCCCv1.1 or higher. This implements v1.0 of the errata ABI spec. For details on all possible return values, refer the design documentation below: ABI design documentation: https://developer.arm.com/documentation/den0100/1-0?lang=en Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com> Change-Id: I70f0e2569cf92e6e02ad82e3e77874546232b89a
* | | Merge changes from topic "bk/context_refactor" into integrationManish V Badarkhe2023-05-091-0/+9
|\ \ \ | |_|/ |/| | | | | | | | | | | * changes: fix(gicv3): restore scr_el3 after changing it refactor(cm): make SVE and SME build dependencies logical
| * | refactor(cm): make SVE and SME build dependencies logicalBoyan Karatotev2023-05-051-0/+9
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, enabling SME forces SVE off. However, the SME enablement requires SVE to be enabled, which is reflected in code. This is the opposite of what the build flags require. Further, the few platforms that enable SME also explicitly enable SVE. Their platform.mk runs after the defaults.mk file so this override never materializes. As a result, the override is only present on the commandline. Change it to something sensible where if SME is on then code can rely on SVE being on too. Do this with a check in the Makefile as it is the more widely used pattern. This maintains all valid use cases but subtly changes corner cases no one uses at the moment to require a slightly different combination of flags. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: If7ca3972ebc3c321e554533d7bc81af49c2472be
* | Merge changes from topic "assert_boolean_set" into integrationManish Pandey2023-05-091-0/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: build!: check boolean flags are not empty fix(build): add a default value for INVERTED_MEMMAP fix(a5ds): add default value for ARM_DISABLE_TRUSTED_WDOG fix(st-crypto): move flag control into source code fix(stm32mp1): always define PKA algos flags fix(stm32mp1): remove boolean check on PLAT_TBBR_IMG_DEF
| * | fix(build): add a default value for INVERTED_MEMMAPYann Gautier2023-05-031-0/+1
| |/ | | | | | | | | | | | | | | It is needed to check the validity of boolean flags with the updated macro assert_boolean. Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I185beb55606a4ca435d2fee2092fc61725859aa1
* | fix(build): allow lower address access with gcc-12Govindraj Raja2023-05-091-0/+4
|/ | | | | | | | | | | | With gcc-12 any lower address access can trigger a warning/error this would be useful in other parts of system but in TF-A there are various reasons to access to the lower address ranges, example using mmio_read_*/writes_* So setup to allow access to lower addresses while using gcc-12 Change-Id: Id1b4012b13bc6876d83b90a347fee12478a1921d Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
* Merge "feat(el3-runtime): handle traps for IMPDEF registers accesses" into ↵Manish Pandey2023-05-021-0/+2
|\ | | | | | | integration
| * feat(el3-runtime): handle traps for IMPDEF registers accessesVarun Wadekar2023-04-301-0/+2
| | | | | | | | | | | | | | | | | | This patch introduces support to handle traps from lower ELs for IMPDEF system register accesses. The actual support is left to the platforms to implement. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I623d5c432b4ce4328b68f238c15b1c83df97c1e5
* | feat(sme): enable SME2 functionality for NS worldJayanth Dodderi Chidanand2023-04-271-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FEAT_SME2 is an extension of FEAT_SME and an optional feature from v9.2. Its an extension of SME, wherein it not only processes matrix operations efficiently, but also provides outer-product instructions to accelerate matrix operations. It affords instructions for multi-vector operations. Further, it adds an 512 bit architectural register ZT0. This patch implements all the changes introduced with FEAT_SME2 to ensure that the instructions are allowed to access ZT0 register from Non-secure lower exception levels. Additionally, it adds support to ensure FEAT_SME2 is aligned with the existing FEATURE DETECTION mechanism, and documented. Change-Id: Iee0f61943304a9cfc3db8f986047b1321d0a6463 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* | feat(gcs): support guarded control stackMark Brown2023-04-181-0/+2
|/ | | | | | | | | | | | | | Arm v9.4 introduces support for Guarded Control Stack, providing mitigations against some forms of RPO attacks and an efficient mechanism for obtaining the current call stack without requiring a full stack unwind. Enable access to this feature for EL2 and below, context switching the newly added EL2 registers as appropriate. Change the FVP platform to default to handling this as a dynamic option so the right decision can be made by the code at runtime. Signed-off-by: Mark Brown <broonie@kernel.org> Change-Id: I691aa7c22e3547bb3abe98d96993baf18c5f0e7b
* feat(pie/por): support permission indirection and overlayMark Brown2023-04-121-0/+8
| | | | | | | | | | | | | | | | | | | Arm v8.9 introduces a series of features providing a new way to set memory permissions. Instead of directly encoding the permissions in the page tables the PTEs contain indexes into an array of permissions stored in system registers, allowing greater flexibility and density of encoding. Enable access to these features for EL2 and below, context switching the newly added EL2 registers as appropriate. Since all of FEAT_S[12]P[IO]E are separately discoverable we have separate build time options for enabling them, but note that there is overlap in the registers that they implement and the enable bit required for lower EL access. Change the FVP platform to default to handling them as dynamic options so the right decision can be made by the code at runtime. Signed-off-by: Mark Brown <broonie@kernel.org> Change-Id: Icf89e444e39e1af768739668b505661df18fb234
* Merge changes from topic "mb/rst-to-bl31-update" into integrationManish V Badarkhe2023-04-111-2/+0
|\ | | | | | | | | | | | | | | * changes: docs: update RESET_TO_BL31 documentation fix(bl31): avoid clearing of argument registers in RESET_TO_BL31 case Revert "docs(bl31): aarch64: RESET_TO_BL31_WITH_PARAMS" Revert "feat(bl31): aarch64: RESET_TO_BL31_WITH_PARAMS"
| * Revert "feat(bl31): aarch64: RESET_TO_BL31_WITH_PARAMS"Manish V Badarkhe2023-03-091-2/+0
| | | | | | | | | | | | | | | | | | Adopted RESET_TO_BL31_WITH_PARAMS functionality in RESET_TO_BL31 in the subsequent patches hence reverted this patch. This reverts commit 25844ff728e4a0e5430ba2032457aba7b780a701. Change-Id: Ia0bfa22fc45754f15c82638662dde93f604992c3 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* | feat(cpufeat): enable FEAT_SVE for FEAT_STATE_CHECKEDJayanth Dodderi Chidanand2023-03-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for runtime detection (ENABLE_SVE_FOR_NS=2), by splitting sve_supported() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we do SVE specific setup. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I1caaba2216e8e2a651452254944a003607503216 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* | feat(cpufeat): enable FEAT_SME for FEAT_STATE_CHECKEDJayanth Dodderi Chidanand2023-03-281-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for runtime detection (ENABLE_SME_FOR_NS=2), by splitting feat_sme_supported() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we do SME specific setup. Change the FVP platform default to the now supported dynamic option (=2),so the right decision can be made by the code at runtime. Change-Id: Ida9ccf737db5be20865b84f42b1f9587be0626ab Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* | Merge changes from topic "psci-osi" into integrationManish Pandey2023-03-281-0/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: feat(sc7280): add support for PSCI_OS_INIT_MODE feat(fvp): enable support for PSCI OS-initiated mode feat(psci): update PSCI_FEATURES feat(psci): add support for OS-initiated mode feat(psci): add support for PSCI_SET_SUSPEND_MODE build(psci): add build option for OS-initiated mode docs(psci): add design proposal for OS-initiated mode
| * | build(psci): add build option for OS-initiated modeWing Li2023-03-201-0/+2
| | | | | | | | | | | | | | | Change-Id: Ie4f7b6a36926ab075ebb9c6507a3ff48ce5538fe Signed-off-by: Wing Li <wingers@google.com>
* | | refactor(amu): unify ENABLE_AMU and ENABLE_FEAT_AMUv1Andre Przywara2023-03-271-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far we have the ENABLE_AMU build option to include AMU register handling code for enabling and context switch. There is also an ENABLE_FEAT_AMUv1 option, solely to protect the HAFGRTR_EL2 system register handling. The latter needs some alignment with the new feature scheme, but it conceptually overlaps with the ENABLE_AMU option. Since there is no real need for two separate options, unify both into a new ENABLE_FEAT_AMU name in a first step. This is mostly just renaming at this point, a subsequent patch will make use of the new feature handling scheme. Change-Id: I97d8a55bdee2ed1e1509fa9f2b09fd0bdd82736e Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | Merge changes from topic "feat_state_part4" into integrationManish Pandey2023-03-271-2/+2
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: refactor(cpufeat): enable FEAT_RNG for FEAT_STATE_CHECKED refactor(cpufeat): align FEAT_SEL2 to new feature handling refactor(cpufeat): enable FEAT_NV2 for FEAT_STATE_CHECKED refactor(cpufeat): enable FEAT_TWED for FEAT_STATE_CHECKED refactor(cpufeat): enable FEAT_CSV2_2 for FEAT_STATE_CHECKED refactor(cpufeat): enable FEAT_ECV for FEAT_STATE_CHECKED refactor(cpufeat): enable FEAT_PAN for FEAT_STATE_CHECKED refactor(cpufeat): align FEAT_SB to new feature handling refactor(cpufeat): use alternative encoding for "SB" barrier refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKED fix(cpufeat): make stub enable functions "static inline" fix(mpam): feat_detect: support major/minor
| * | | refactor(cpufeat): align FEAT_SB to new feature handlingAndre Przywara2023-03-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FEAT_SB introduces a new speculation barrier instruction, that is more lightweight than a "dsb; isb" combination. We use that in a hot path, so cannot afford and don't want a runtime detection mechanism. Nevertheless align the implementation of the feature detection part with the other features, but renaming the detection function, and updating the FEAT_DETECTION code. Also update the documentation. Change-Id: I2b86dfd1ad259c3bb99ab5186e2911ace454b54c Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKEDAndre Przywara2023-03-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support access to the trace unit by system registers (SYS_REG_TRACE) to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_SYS_REG_TRACE_FOR_NS=2), by adding is_feat_sys_reg_trace_supported(). That function considers both build time settings and runtime information (if needed), and is used before we access SYS_REG_TRACE related registers. The FVP platform decided to compile in support unconditionally (=1), even though this is an optional feature, so it is not available with the FVP model's default command line. Change that to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I450a574a4f6bd9fc269887037049c94c906f54b2 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | | Merge "fix(pauth): make pauth_helpers linking generic" into integrationManish Pandey2023-03-211-0/+7
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| * | | fix(pauth): make pauth_helpers linking genericBoyan Karatotev2023-02-281-0/+7
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | Pauth is a generic Arm feature that can be enabled on any platform that implements it. It only needs a platform specific key generation hook. As such, the generic Pauth enablement can be included in the generic build. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: Ibf32f79addab3515214594bb8d7168151b450f59
* | | refactor(spe): enable FEAT_SPE for FEAT_STATE_CHECKEDAndre Przywara2023-03-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_SPE to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_SPE_FOR_NS=2), by splitting is_armv8_2_feat_spe_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access SPE related registers. Previously SPE was enabled unconditionally for all platforms, change this now to the runtime detection version. Change-Id: I830c094107ce6a398bf1f4aef7ffcb79d4f36552 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | refactor(cpufeat): rename ENABLE_SPE_FOR_LOWER_ELS to ENABLE_SPE_FOR_NSAndre Przywara2023-03-201-2/+2
| |/ |/| | | | | | | | | | | | | | | | | | | | | At the moment we hardcode the SPE functionality to be available on the non-secure side only, by setting MDCR_EL2.E2PB accordingly. This should be reflected in the feature selection symbol, so rename that to ENABLE_SPE_FOR_NS, to make it clearer that SPE is not supported in the secure world. Change-Id: I3f9b48eab1a45d6ccfcbb9c90a11eeb66867ad9a Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | Merge "feat(tcr2): support FEAT_TCR2" into integrationManish Pandey2023-03-171-0/+2
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| * | feat(tcr2): support FEAT_TCR2Mark Brown2023-03-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Arm v8.9 introduces FEAT_TCR2, adding extended translation control registers. Support this, context switching TCR2_EL2 and disabling traps so lower ELs can access the new registers. Change the FVP platform to default to handling this as a dynamic option so the right decision can be made by the code at runtime. Signed-off-by: Mark Brown <broonie@kernel.org> Change-Id: I297452acd8646d58bac64fc15e05b06a543e5148
* | | Merge "refactor(build): distinguish BL2 as TF-A entry point and BL2 running ↵Manish Pandey2023-03-151-8/+25
|\ \ \ | |/ / |/| | | | | at EL3" into integration
| * | refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3Arvind Ram Prakash2023-03-151-8/+25
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BL2_AT_EL3 is an overloaded macro which has two uses: 1. When BL2 is entry point into TF-A(no BL1) 2. When BL2 is running at EL3 exception level These two scenarios are not exactly same even though first implicitly means second to be true. To distinguish between these two use cases we introduce new macros. BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2. Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where BL2 runs at EL3 (including four world systems). BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the repository. Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
* | feat(build): add support for new binutils versionsMarco Felsch2023-03-131-0/+5
|/ | | | | | | | | | | | | | | | | | | | | | | | | Users of GNU ld (BPF) from binutils 2.39+ will observe multiple instaces of a new warning when linking the bl*.elf in the form: ld.bfd: warning: stm32mp1_helper.o: missing .note.GNU-stack section implies executable stack ld.bfd: NOTE: This behaviour is deprecated and will be removed in a future version of the linker ld.bfd: warning: bl2.elf has a LOAD segment with RWX permissions ld.bfd: warning: bl32.elf has a LOAD segment with RWX permissions These new warnings are enbaled by default to secure elf binaries: - https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=ba951afb99912da01a6e8434126b8fac7aa75107 - https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=0d38576a34ec64a1b4500c9277a8e9d0f07e6774 Fix it in a similar way to what the Linux kernel does, see: https://lore.kernel.org/all/20220810222442.2296651-1-ndesaulniers@google.com/ Following the reasoning there, we set "-z noexecstack" for all linkers (although LLVM's LLD defaults to it) and optional add --no-warn-rwx-segments since this a ld.bfd related. Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Robert Schwebel <r.schwebel@pengutronix.de> Change-Id: I9430f5fa5036ca88da46cd3b945754d62616b617
* build: communicate correct page size to linkerChris Kay2023-02-151-0/+8
| | | | | | | | | | | | | This change communicates the common and maximum page sizes to the linker, which allows us to use the built-in constants that it provides to deal with page alignments. We only support 4K pages today so the fact these are fixed is not too much of an issue, but we will need to revisit this if we ever support other page sizes. Change-Id: I3358c51e70df794025ddf25209ae0e2a96550b0e Signed-off-by: Chris Kay <chris.kay@arm.com>
* Merge "fix(build): allow warnings when using lld" into integrationManish Pandey2023-02-141-3/+5
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| * fix(build): allow warnings when using lldYabin Cui2023-01-191-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After https://reviews.llvm.org/D118840, ld.lld reports below section type mismatch warnings: LD trusted-firmware-a/build/qemu/release/bl1/bl1.elf ld.lld: error: section type mismatch for base_xlat_table >>> trusted-firmware-a/build/qemu/release/bl1/xlat_tables_context.o: (base_xlat_table): SHT_PROGBITS >>> output section .bss: SHT_NOBITS ld.lld: error: section type mismatch for xlat_table >>> trusted-firmware-a/build/qemu/release/bl1/xlat_tables_context.o: (xlat_table): SHT_PROGBITS >>> output section xlat_table: SHT_NOBITS So allow warnings to make build pass. Change-Id: I70503ad03b3be7a18ffe29ef6f2127c3f4d540f1 Signed-off-by: Yabin Cui <yabinc@google.com>
* | fix(pie): pass `-fpie` to the preprocessor as wellChris Kay2023-02-101-1/+5
| | | | | | | | | | | | | | | | | | | | When PIE is enabled, the `-fpie` flag is passed to the compiler but not to the preprocessor. This change ensures that both tools are aware of when the image is position-independent when preprocessing, which impacts some pre-defined preprocessor definitions. Change-Id: I5208a591d60ee01312f6bf3dd7343abe6535ee61 Signed-off-by: Chris Kay <chris.kay@arm.com>
* | fix(context-mgmt): enable SCXTNUM accessMaksims Svecovs2023-02-091-1/+4
|/ | | | | | | | | Enable SCXTNUM_ELx access for lower ELs in non-secure state. Make realm context setup take this build flag into account but enable it by default when RME is used. Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com> Change-Id: Ieb0186b2fdffad464bb9316fc3973772c9c28cd0
* Merge changes from topic "bk/warnings" into integrationManish Pandey2023-01-101-12/+38
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: docs: describe the new warning levels build: add -Wunused-const-variable=2 to W=2 build: include -Wextra in generic builds docs(porting-guide): update a reference fix(st-usb): replace redundant checks with asserts fix(brcm): add braces around bodies of conditionals fix(renesas): align incompatible function pointers fix(zynqmp): remove redundant api_version check fix: remove old-style declarations fix: unify fallthrough annotations
| * build: add -Wunused-const-variable=2 to W=2Boyan Karatotev2022-12-011-0/+2
| | | | | | | | | | | | | | | | | | TF-A is quite strict with warnings and redundant code. This flag furthers this so it would be useful to have it. Add it to W=2 as it sets off a few platforms which require a somewhat involved fix. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: Id52b3d477b4ada7dd69a36101ab22c575ab4ef19
| * build: include -Wextra in generic buildsBoyan Karatotev2022-12-011-12/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TF-A is more strict with compiler warnings in comparison to other projects (notably Linux) for security and -Wextra enables a lot of desirable warnings. This patch enables -Wextra by default (from W=1 previously) and reorganises the warning levels so that they can useful when enabled and not just a build failure. This will help us move towards fixing the warnings that are too many to fix at once and enabling all W={1, 2} warnings. The warning levels get new meanings: * W=1: warnings we want the generic build to include but are too time consuming to fix at the moment. They re-enable warnings taken out for generic builds. * W=2: warnings we want the generic build to include but cannot be enabled due to external libraries. * W=3: warnings that are informative but not necessary and generally too verbose and frequently ignored. Quality expectations for new contributions mean that generally they should have no warnings up to W=2. To allow code to be developed with them in mind, -Werror is disabled when W=x is set. This way enabling warnings will not just fail the build due to technicalities we have and contributors will be able to actually see if they get any. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: Ieb15ddd635d458a956a34b0f9d0ea2f81b9c0745
* | build: restrict usage of CTX_INCLUDE_EL2_REGSGovindraj Raja2022-12-011-3/+9
|/ | | | | | | | | | | CTX_INCLUDE_EL2_REGS is used to save/restore EL2 registers and it should be only used when there is SPMD or RME enabled. Make CTX_INCLUDE_EL2_REGS an internal macro and remove from documentation. Signed-off-by: Govindraj Raja <govindraj.raja@arm.com> Change-Id: I6a70edfd88163423ff0482de094601cf794246d6
* docs(changelog): changelog for v2.8 releaselaurenw-arm2022-11-161-1/+1
| | | | | Change-Id: I1d99ea46ad527993ee786c34a67f94d74470f960 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
* fix(build): ensure that the correct rule is called for toolsLionel Debieve2022-11-141-3/+3
| | | | | | | | | In case of platform specific usage for both fiptool or certtool, we need to ensure that the Makefile will use the correct rule to generate the binary. Add the explicit call to the "all" rule. Change-Id: I9724b63e01b3497daaedb9365c7d6a494aac9561 Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
* Merge "refactor(security): add OpenSSL 1.x compatibility" into integrationManish V Badarkhe2022-11-111-3/+3
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| * refactor(security): add OpenSSL 1.x compatibilityJuan Pablo Conde2022-11-111-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When updated to work with OpenSSL 3.0, the host tools lost their compatibility with previous versions (1.x) of OpenSSL. This is mainly due to the fact that 1.x APIs became deprecated in 3.0 and therefore their use cause compiling errors. In addition, updating for a newer version of OpenSSL meant improving the stability against security threats. However, although version 1.1.1 is now deprecated, it still receives security updates, so it would not imply major security issues to keep compatibility with it too. This patch adds backwards compatibility with OpenSSL 1.x versions by adding back 1.x API code. It defines a macro USING_OPENSSL3, which will select the appropriate OpenSSL API version depending on the OpenSSL library path chosen (which is determined by the already-existing OPENSSL_DIR variable). In addition, cleanup items were packed in functions and moved to the proper modules in order to make the code more maintainable and legible. Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com> Change-Id: I8deceb5e419edc73277792861882404790ccd33c
* | Merge "feat(cpus): make cache ops conditional" into integrationBipin Ravi2022-11-111-0/+2
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| * | feat(cpus): make cache ops conditionalOkash Khawaja2022-11-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a core is in debug recovery mode its caches are not invalidated upon reset, so the L1 and L2 cache contents from before reset are observable after reset. Similarly, debug recovery mode of DynamIQ cluster ensures that contents of the shared L3 cache are also not invalidated upon transition to On mode. Booting cores in debug recovery mode means booting with caches disabled and preserving the caches until a point where software can dump the caches and retrieve their contents. TF-A however unconditionally cleans and invalidates caches at multiple points during boot. This can lead to memory corruption as well as loss of cache contents to be used for debugging. This patch fixes this by calling a platform hook before performing CMOs in helper routines in cache_helpers.S. The platform hook plat_can_cmo is an assembly routine which must not clobber x2 and x3, and avoid using stack. The whole checking is conditional upon `CONDITIONAL_CMO` which can be set at compile time. Signed-off-by: Okash Khawaja <okash@google.com> Change-Id: I172e999e4acd0f872c24056e647cc947ee54b193
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