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* feat(debug): add helpers for aborts on AARCH32Yann Gautier2022-10-031-3/+3
| | | | | | | | | | | | | | | | New helper functions are created to handle data & prefetch aborts in AARCH32. They call platform functions, just like what report_exception is doing. As extended MSR/MRS instructions (to access lr_abt in monitor mode) are only available if CPU (Armv7) has virtualization extension, the functions branch to original report_exception handlers if this is not the case. Those new helpers are created mainly to distinguish data and prefetch aborts, as they both share the same mode. This adds 40 bytes of code. Change-Id: I5dd31930344ad4e3a658f8a9d366a87a300aeb67 Signed-off-by: Yann Gautier <yann.gautier@st.com>
* Avoid the use of linker *_SIZE__ macrosYann Gautier2021-04-211-2/+3
| | | | | | | | | | | | | | The use of end addresses is preferred over the size of sections. This was done for some AARCH64 files for PIE with commit [1], and some extra explanations can be found in its commit message. Align the missing AARCH64 files. For AARCH32 files, this is required to prepare PIE support introduction. [1] f1722b693d36 ("PIE: Use PC relative adrp/adr for symbol reference") Change-Id: I8f1c06580182b10c680310850f72904e58a54d7d Signed-off-by: Yann Gautier <yann.gautier@st.com>
* Apply stricter speculative load restrictionJohn Tsichritzis2019-03-121-4/+5
| | | | | | | | | | | The SCTLR.DSSBS bit is zero by default thus disabling speculative loads. However, we also explicitly set it to zero for BL2 and TSP images when each image initialises its context. This is done to ensure that the image environment is initialised in a safe state, regardless of the reset value of the bit. Change-Id: If25a8396641edb640f7f298b8d3309d5cba3cd79 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* Sanitise includes across codebaseAntonio Nino Diaz2019-01-041-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Fix BL2U entrypoint possible parameter corruptionDouglas Raillard2017-08-021-2/+2
| | | | | | | | | | | | Replace the use of r12 by r10 to save the value of a parameter of bl2u_entrypoint to pass it to bl2u_early_platform_setup at the end of the function. r10 is a callee saved register so it will not become corrupted by C code, whereas r12 is the The Intra-Procedure-call scratch register potentially used by veneers. See the ARM AAPCS document (ARM IHI 0042F). Change-Id: I4f37e54a6b550719edb40bb24cd8f498827e2749 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
* AArch32: Add BL2U supportYatharth Kochar2017-05-151-0/+126
Add support for firmware upgrade on AArch32. This patch has been tested on the FVP models. NOTE: Firmware upgrade on Juno AArch32 is not currently supported. Change-Id: I1ca8078214eaf86b46463edd14740120af930aec Signed-off-by: dp-arm <dimitris.papastamos@arm.com> Co-Authored-By: Yatharth Kochar <yatharth.kochar@arm.com>