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* refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKEDAndre Przywara2023-05-091-11/+1
| | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_RAS to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (FEAT_RAS=2), by splitting is_armv8_2_feat_ras_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access RAS related registers. Also move the context saving code from assembly to C, and use the new is_feat_ras_supported() function to guard its execution. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I30498f72fd80b136850856244687400456a03d0e Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
* refactor(ras): replace RAS_EXTENSION with FEAT_RASManish Pandey2023-05-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current usage of RAS_EXTENSION in TF-A codebase is to cater for two things in TF-A : 1. Pull in necessary framework and platform hooks for Firmware first handling(FFH) of RAS errors. 2. Manage the FEAT_RAS extension when switching the worlds. FFH means that all the EAs from NS are trapped in EL3 first and signaled to NS world later after the first handling is done in firmware. There is an alternate way of handling RAS errors viz Kernel First handling(KFH). Tying FEAT_RAS to RAS_EXTENSION build flag was not correct as the feature is needed for proper handling KFH in as well. This patch breaks down the RAS_EXTENSION flag into a flag to denote the CPU architecture `ENABLE_FEAT_RAS` which is used in context management during world switch and another flag `RAS_FFH_SUPPORT` to pull in required framework and platform hooks for FFH. Proper support for KFH will be added in future patches. BREAKING CHANGE: The previous RAS_EXTENSION is now deprecated. The equivalent functionality can be achieved by the following 2 options: - ENABLE_FEAT_RAS - RAS_FFH_SUPPORT Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I1abb9ab6622b8f1b15712b12f17612804d48a6ec
* feat(sme): enable SME2 functionality for NS worldJayanth Dodderi Chidanand2023-04-271-0/+2
| | | | | | | | | | | | | | | | | | | FEAT_SME2 is an extension of FEAT_SME and an optional feature from v9.2. Its an extension of SME, wherein it not only processes matrix operations efficiently, but also provides outer-product instructions to accelerate matrix operations. It affords instructions for multi-vector operations. Further, it adds an 512 bit architectural register ZT0. This patch implements all the changes introduced with FEAT_SME2 to ensure that the instructions are allowed to access ZT0 register from Non-secure lower exception levels. Additionally, it adds support to ensure FEAT_SME2 is aligned with the existing FEATURE DETECTION mechanism, and documented. Change-Id: Iee0f61943304a9cfc3db8f986047b1321d0a6463 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* refactor(cpufeat): enable FEAT_DIT for FEAT_STATE_CHECKEDAndre Przywara2023-04-251-11/+1
| | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_DIT to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_DIT=2), by splitting is_armv8_4_dit_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed). We use ENABLE_DIT in two occassions in assembly code, where we just set the DIT bit in the DIT system register. Protect those two cases by reading the CPU ID register when ENABLE_DIT is set to 2. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I506d352f18e23c60db8cdf08edb449f60adbe098 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* Merge "feat(gcs): support guarded control stack" into integrationBipin Ravi2023-04-251-0/+4
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| * feat(gcs): support guarded control stackMark Brown2023-04-181-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Arm v9.4 introduces support for Guarded Control Stack, providing mitigations against some forms of RPO attacks and an efficient mechanism for obtaining the current call stack without requiring a full stack unwind. Enable access to this feature for EL2 and below, context switching the newly added EL2 registers as appropriate. Change the FVP platform to default to handling this as a dynamic option so the right decision can be made by the code at runtime. Signed-off-by: Mark Brown <broonie@kernel.org> Change-Id: I691aa7c22e3547bb3abe98d96993baf18c5f0e7b
* | fix(uuid): add missing `#include` directivesChris Kay2023-04-171-2/+1
|/ | | | | | | These include directives were missing from both `uuid.h` files. Change-Id: I875dfda3e0985728277b72f0e7597dde5cf9d304 Signed-off-by: Chris Kay <chris.kay@arm.com>
* feat(pie/por): support permission indirection and overlayMark Brown2023-04-121-0/+8
| | | | | | | | | | | | | | | | | | | Arm v8.9 introduces a series of features providing a new way to set memory permissions. Instead of directly encoding the permissions in the page tables the PTEs contain indexes into an array of permissions stored in system registers, allowing greater flexibility and density of encoding. Enable access to these features for EL2 and below, context switching the newly added EL2 registers as appropriate. Since all of FEAT_S[12]P[IO]E are separately discoverable we have separate build time options for enabling them, but note that there is overlap in the registers that they implement and the enable bit required for lower EL access. Change the FVP platform to default to handling them as dynamic options so the right decision can be made by the code at runtime. Signed-off-by: Mark Brown <broonie@kernel.org> Change-Id: Icf89e444e39e1af768739668b505661df18fb234
* feat(cpufeat): enable FEAT_SVE for FEAT_STATE_CHECKEDJayanth Dodderi Chidanand2023-03-281-0/+2
| | | | | | | | | | | | | | Add support for runtime detection (ENABLE_SVE_FOR_NS=2), by splitting sve_supported() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we do SVE specific setup. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I1caaba2216e8e2a651452254944a003607503216 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* feat(cpufeat): enable FEAT_SME for FEAT_STATE_CHECKEDJayanth Dodderi Chidanand2023-03-281-1/+3
| | | | | | | | | | | | | | Add support for runtime detection (ENABLE_SME_FOR_NS=2), by splitting feat_sme_supported() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we do SME specific setup. Change the FVP platform default to the now supported dynamic option (=2),so the right decision can be made by the code at runtime. Change-Id: Ida9ccf737db5be20865b84f42b1f9587be0626ab Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* refactor(amu): use new AMU feature check routinesAndre Przywara2023-03-271-11/+2
| | | | | | | | | The AMU extension code was using its own feature detection routines. Replace them with the generic CPU feature handlers (defined in arch_features.h), which get updated to cover the v1p1 variant as well. Change-Id: I8540f1e745d7b02a25a6c6cdf2a39d6f5e21f2aa Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* refactor(amu): unify ENABLE_AMU and ENABLE_FEAT_AMUv1Andre Przywara2023-03-271-1/+1
| | | | | | | | | | | | | | | | So far we have the ENABLE_AMU build option to include AMU register handling code for enabling and context switch. There is also an ENABLE_FEAT_AMUv1 option, solely to protect the HAFGRTR_EL2 system register handling. The latter needs some alignment with the new feature scheme, but it conceptually overlaps with the ENABLE_AMU option. Since there is no real need for two separate options, unify both into a new ENABLE_FEAT_AMU name in a first step. This is mostly just renaming at this point, a subsequent patch will make use of the new feature handling scheme. Change-Id: I97d8a55bdee2ed1e1509fa9f2b09fd0bdd82736e Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* refactor(cpufeat): enable FEAT_RNG for FEAT_STATE_CHECKEDAndre Przywara2023-03-221-11/+1
| | | | | | | | | | | | | | | | | At the moment we only support for FEAT_RNG to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (FEAT_RNG=2), by splitting is_armv8_5_rng_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access the RNDRRS system register. Change the QEMU platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I1a4a538d5ad395fead7324f297d0056bda4f84cb Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* refactor(cpufeat): align FEAT_SEL2 to new feature handlingAndre Przywara2023-03-221-11/+2
| | | | | | | | | In ARMv8.4, the EL2 exception level got added to the secure world. Adapt and rename the existing is_armv8_4_sel2_present() function, to align its handling with the other CPU features. Change-Id: If11e1942fdeb63c63f36ab9e89be810347d1a952 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* refactor(cpufeat): enable FEAT_NV2 for FEAT_STATE_CHECKEDAndre Przywara2023-03-221-13/+2
| | | | | | | | | | | | | | | | | | | At the moment we only support for FEAT_NV2 to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (CTX_INCLUDE_NEVE_REGS=2), by splitting get_armv8_4_feat_nv_support() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access the VNCR_EL2 system register. Also move the context saving code from assembly to C, and use the new is_feat_nv2_supported() function to guard its execution. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I85b080641995fb72cfd4ac933f7a3f75770c2cb9 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* refactor(cpufeat): enable FEAT_TWED for FEAT_STATE_CHECKEDAndre Przywara2023-03-221-11/+2
| | | | | | | | | | | | | | | | | At the moment we only support FEAT_TWED to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_FEAT_TWED=2), by splitting is_armv8_6_twed_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we set the trap delay time. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I58626230ef0af49886c0a197abace01e81f661d2 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* refactor(cpufeat): enable FEAT_CSV2_2 for FEAT_STATE_CHECKEDAndre Przywara2023-03-221-11/+2
| | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_CSV2_2 to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_FEAT_CSV2_2=2), by splitting is_armv8_0_feat_csv2_2_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access the SCXTNUM_EL2 system register. Also move the context saving code from assembly to C, and use the new is_feat_csv2_2_supported() function to guard its execution. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I89c7bc883e6a65727fdbdd36eb3bfbffb2196da7 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* refactor(cpufeat): enable FEAT_ECV for FEAT_STATE_CHECKEDAndre Przywara2023-03-221-14/+1
| | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_ECV to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_FEAT_ECV=2), by splitting is_feat_ecv_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access the CNTPOFF_EL2 system register. Also move the context saving code from assembly to C, and use the new is_feat_ecv_supported() function to guard its execution. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I4acd5384929f1902b62a87ae073aafa1472cd66b Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* refactor(cpufeat): enable FEAT_PAN for FEAT_STATE_CHECKEDAndre Przywara2023-03-221-11/+1
| | | | | | | | | | | | | | | | | At the moment we only support FEAT_PAN to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_FEAT_PAN=2), by splitting is_armv8_1_pan_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we PAN specific setup. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I58e5fe8d3c9332820391c7d93a8fb9dba4cf754a Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* refactor(cpufeat): align FEAT_SB to new feature handlingAndre Przywara2023-03-221-11/+1
| | | | | | | | | | | | FEAT_SB introduces a new speculation barrier instruction, that is more lightweight than a "dsb; isb" combination. We use that in a hot path, so cannot afford and don't want a runtime detection mechanism. Nevertheless align the implementation of the feature detection part with the other features, but renaming the detection function, and updating the FEAT_DETECTION code. Also update the documentation. Change-Id: I2b86dfd1ad259c3bb99ab5186e2911ace454b54c Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* fix(mpam): feat_detect: support major/minorAndre Przywara2023-03-211-1/+1
| | | | | | | | | | | | | | | The MPAM CPU ID version number is split between two CPU ID register fields, with the second being a fractional field, allowing for instance for a "MPAM v1.1" number. The read_feat_mpam_version() function merges those two fields to form a "4.4" fixed point fractional number, but the limit check in the check_feature() function was not taking this into account. To support MPAM major version 1, extend the limit from "1" to "17", to cover the current maximum version of "MPAM v1.1". This fixes FVP runs with "has_mpam=1" and FEATURE_DETECTION enabled. Change-Id: Icb557741d597e4e43eaf658b78f18af6e9fb439e Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* refactor(cpufeat): enable FEAT_VHE for FEAT_STATE_CHECKEDAndre Przywara2023-03-201-11/+1
| | | | | | | | | | | | | | | | | | At the moment we only support FEAT_VHE to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_FEAT_VHE=2), by splitting is_armv8_1_vhe_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access VHE related registers. Also move the context saving code from assembly to C, and use the new is_feat_vhe_supported() function to guard its execution. Enable VHE in its runtime detection version for all FVP builds. Change-Id: Ib397cd0c83e8c709bd6fed603560e39901fa672b Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* refactor(mpam): enable FEAT_MPAM for FEAT_STATE_CHECKEDAndre Przywara2023-03-201-11/+2
| | | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_MPAM to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_MPAM_FOR_LOWER_ELS=2), by splitting get_mpam_version() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access MPAM related registers. Also move the context saving code from assembly to C, and use the new is_feat_mpam_supported() function to guard its execution. ENABLE_MPAM_FOR_LOWER_ELS defaults to 0, so add a stub enable function to cover builds with compiler optimisations turned off. The unused mpam_enable() function call will normally be optimised away (because it would never be called), but with -O0 the compiler will leave the symbol in the object file. Change-Id: I531d87cb855a7c43471f861f625b5a6d4bc61313 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* feat(tcr2): support FEAT_TCR2Mark Brown2023-03-161-0/+4
| | | | | | | | | | | | Arm v8.9 introduces FEAT_TCR2, adding extended translation control registers. Support this, context switching TCR2_EL2 and disabling traps so lower ELs can access the new registers. Change the FVP platform to default to handling this as a dynamic option so the right decision can be made by the code at runtime. Signed-off-by: Mark Brown <broonie@kernel.org> Change-Id: I297452acd8646d58bac64fc15e05b06a543e5148
* refactor(trf): enable FEAT_TRF for FEAT_STATE_CHECKEDAndre Przywara2023-02-271-11/+2
| | | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_TRF to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_TRF_FOR_NS=2), by splitting is_feat_trf_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access TRF related registers. Also move the context saving code from assembly to C, and use the new is_feat_trf_supported() function to guard its execution. The FVP platform decided to compile in support unconditionally (=1), even though FEAT_TRF is an ARMv8.4 feature, so is not available with the FVP model's default command line. Change that to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: Ia97b01adbe24970a4d837afd463dc5506b7295a3 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* refactor(brbe): enable FEAT_BRBE for FEAT_STATE_CHECKEDAndre Przywara2023-02-271-11/+2
| | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_BRBE to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_BRBE_FOR_NS=2), by splitting is_feat_brbe_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access BRBE related registers. The FVP platform decided to compile in support unconditionally (=1), even though FEAT_BRBE is an ARMv9 feature, so is not available with the FVP model's default command line. Change that to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I5f2e2c9648300f65f0fa9a5f8e2f34e73529d053 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* refactor(trbe): enable FEAT_TRBE for FEAT_STATE_CHECKEDAndre Przywara2023-02-271-11/+2
| | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_TRBE to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_TRBE_FOR_NS=2), by splitting is_feat_trbe_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access TRBE related registers. The FVP platform decided to compile in support unconditionally (=1), even though FEAT_TRBE is an ARMv9 feature, so is not available with the FVP model's default command line. Change that to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: Iee7f88ea930119049543a8a4a105389997e7692c Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* feat(cpufeat): extend check_feature() to deal with min/maxAndre Przywara2023-02-271-7/+17
| | | | | | | | | | | | | | | | | So far the check_feature() function compares the subfield of a CPU ID register against 0, to learn if a feature is enabled or not. This is problematic for checks that require a certain revision of a feature, so we should check against a minimum version number instead. On top of that we might need to add code to support newer versions of a feature, so we should be alerted if new hardware introduces a higher number. Extend the check_feature() function to take two extra arguments: the minimum version, and the greatest currently known number. Then make sure that the CPU ID field is in this range. Change-Id: I425b68535a2ba9eafd31854e74d142183b521cd5 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* refactor(bl31): use elx_panic for sysreg_handler64Govindraj Raja2023-02-221-1/+11
| | | | | | | | | | | | When we reach sysreg_handler64 from any trap handling we are entering this path from lower EL and thus we should be calling lower_el_panic reporting mechanism to print panic report. Make report_elx_panic available through assembly func elx_panic which could be used for reporting any lower_el_panic. Change-Id: Ieb260cf20ea327a59db84198b2c6a6bfc9ca9537 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
* refactor(aarch64): rename do_panic and el3_panicGovindraj Raja2023-02-212-15/+8
| | | | | | | | | | | Current panic call invokes do_panic which calls el3_panic, but now panic handles only panic from EL3 anid clear separation to use lower_el_panic() which handles panic from lower ELs. So now we can remove do_panic and just call el3_panic for all panics. Change-Id: I739c69271b9fb15c1176050877a9b0c0394dc739 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
* refactor(aarch64): remove weak links to el3_panicGovindraj Raja2023-02-211-7/+6
| | | | | | | | | | | | | Cleanup weak links to el3_panic and restrict crash_reporting usage to bl31. Crash reporting is not used with bl1, bl2 and weak linkage to el3_panic is used, this can cause ambiguity in understanding the code so remove this weak linkage and introduce funcs that should be used when we have crash reporting for el3 panics. Change-Id: Ic5c711143ba36898ef9574a078b8fa02effceb12 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
* refactor(aarch64): refactor usage of elx_panicGovindraj Raja2023-02-211-22/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we call el3_panic for panics from EL3 and elx_panic for panics from lower ELs. When we boot into a rich OS environment and interact with BL31 using SMC/ABI calls and we can also decide to handle any lower EL panics in EL3. Panic can occur in lower EL from rich OS or during SMC/ABI calls after context switch to EL3. But after booting into any rich OS we may land in panic either from rich OS or while servicing any SMC call, here the logic to use el3_panic or elx_panic is flawed as spsr_el3[3:0] is always EL3h and end up in elx_panic even if panic occurred from EL3 during SMC handling. We try to decouple the elx_panic usage for its intended purpose, introduce lower_el_panic which would call elx_panic, currently lower_el_panic is called from default platform_ea_handle which would be called due to panic from any of the lower ELs. Also remove the weak linkage for elx_panic and rename it to report_elx_panic which could be used with lower_el_panic. Change-Id: I268bca89c01c60520d127ef6c7ba851460edc747 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
* Merge changes from topic "fix_sparse_warnings" into integrationMadhukar Pappireddy2023-01-201-6/+6
|\ | | | | | | | | | | | | | | | | * changes: fix(libc): remove __putchar alias fix(console): correct scopes for console symbols fix(auth): use NULL instead of 0 for pointer check fix(io): compare function pointers with NULL fix(fdt-wrappers): use correct prototypes
| * fix(fdt-wrappers): use correct prototypesYann Gautier2023-01-101-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These issues were triggered by sparse tool: common/fdt_wrappers.c:209:36: warning: incorrect type in assignment (different base types) expected unsigned long long [usertype] got restricted fdt64_t common/fdt_wrappers.c:211:36: warning: incorrect type in assignment (different base types) expected unsigned int [usertype] got restricted fdt32_t common/fdt_wrappers.c:401:45: warning: incorrect type in argument 1 (different base types) expected restricted fdt32_t const [usertype] *prop got unsigned int const [usertype] *value common/fdt_wrappers.c:402:52: warning: incorrect type in argument 1 (different base types) expected restricted fdt32_t const [usertype] *prop got unsigned int const [usertype] * common/fdt_wrappers.c:404:66: warning: incorrect type in argument 1 (different base types) expected restricted fdt32_t const [usertype] *prop got unsigned int const [usertype] * Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I32067607cd4da1897f0ce5d8e1e2d51e044ab815
* | refactor(cpufeat): convert FEAT_HCX to new schemeAndre Przywara2023-01-111-11/+1
| | | | | | | | | | | | | | | | Use the generic check function in feat_detect.c, and split the feature check into two functions, as done for FEAT_FGT before. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: I0a4f973427c10d5d15c414ff5e12b18b7e645fae
* | refactor(amu): convert FEAT_AMUv1 to new schemeAndre Przywara2023-01-111-11/+1
| | | | | | | | | | | | | | | | | | | | For the FGT context save/restore operation, we need to look at the AMUv1 feature, so migrate this one over to the new scheme. This uses the generic check function in feat_detect.c, and splits the feature check into two functions, as was done before for FEAT_FGT. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: I95ad797f15001b2c9d1800c9d4af33fba79e136f
* | refactor(cpufeat): decouple FGT feature detection and build flagsAndre Przywara2023-01-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split the feature check for FEAT_FGT into two parts: - A boolean function that just evaluates whether the feature is usable. This takes build time flags into account, and only evaluates the CPU feature ID registers when the flexible FEAT_STATE_CHECK method is used. - A "raw" function that returns the unfiltered CPU feature ID register. Change the callers where needed, to give them the version they actually want. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: I9a041132d280451f5d9f653a62904f603b2a916d
* | refactor(cpufeat): check FEAT_FGT in a new wayAndre Przywara2023-01-111-11/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To implement proper runtime checking of features, and to be able to extend feat_detect.c to catch other cases, rework the FEAT_FGT check to directly call a generic function instead of providing a trivial specific one. The #ifdef is moved into the function, and rewritten as a proper C if statement. We need to force the compiler to inline that function, otherwise the optimisation won't work, once we exceed a certain number of callers. This starts with FEAT_FGT, but all the other features will be moved over eventually, in separate patches. For all features checked this way, we delay the panic() until after every feature has been checked, to list them all during one run. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: Ic576922ff2c4f8d3c1b87b5843b3626729fe4514
* | refactor(cpufeat): move helpers into .c file, rename FEAT_STATE_Andre Przywara2023-01-111-28/+44
|/ | | | | | | | | | | | | | | | | | | | The FEATURE_DETECTION functionality had some definitions in a header file, although they were only used internally in the .c file. Move them over there, since there are of no interest to other users. Also use the opportuntiy to rename the less telling FEAT_STATE_[12] names, and let the "0" case join the game. We use DISABLED, ALWAYS, and CHECK now, so that the casual reader has some idea what those numbers are supposed to mean. feature_panic() becomes "static inline", since disabling all features makes it unused, so the compiler complains otherwise. Finally add a new category "cpufeat" to cover CPU feature related changes. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: If0c8ba91ad22440260ccff383c33bdd055eefbdc
* fix(ras): restrict RAS support for NS worldManish Pandey2022-11-081-2/+2
| | | | | | | | | | | | | | | Current RAS framework in TF-A only supports handling errors originating from NS world but the HANDLE_EA_EL3_FIRST flag configures it for all lower Els. To make the current design of RAS explicit, rename this macro to HANDLE_EA_EL3_FIRST_NS and set EA bit in scr_el3 only when switching to NS world. Note: I am unaware of any platform which traps errors originating in Secure world to EL3, if there is any such platform then it need to be explicitly implemented in TF-A Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: If58eb201d8fa792c16325c85c26056e9b409b750
* fix(debug): decouple "get_el_str()" from backtraceManish Pandey2022-11-081-11/+0
| | | | | | | | | | | | | get_el_str() was implemented under ENABLE_BACKTRACE macro but being used at generic places too, this causes multiple definition of this function. Remove duplicate definition of this function and move it out of backtrace scope. Also, this patch fixes a small bug where in default case S-EL1 is returned which ideally should be EL1, as there is no notion of security state in EL string. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ib186ea03b776e2478eff556065449ebd478c3538
* Merge "fix: backtrace stack unwind misses lr adjustment" into integrationManish Pandey2022-10-121-20/+24
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| * fix: backtrace stack unwind misses lr adjustmentOlivier Deprez2022-10-051-20/+24
| | | | | | | | | | | | | | | | | | | | | | | | When pointer authentication is used the frame record return address includes the pointer authentication code hence it must be masked out when willing to compare the pointer value with another address or checking its validity. The stack unwind function missed one case of adjusting the return address leading to a misinterpreted corrupted stack frame error message. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I435140937d5fd0f43da27c77d96056b7606d87e9
* | feat(debug): add helpers for aborts on AARCH32Yann Gautier2022-10-031-1/+33
|/ | | | | | | | | | | | | | | | New helper functions are created to handle data & prefetch aborts in AARCH32. They call platform functions, just like what report_exception is doing. As extended MSR/MRS instructions (to access lr_abt in monitor mode) are only available if CPU (Armv7) has virtualization extension, the functions branch to original report_exception handlers if this is not the case. Those new helpers are created mainly to distinguish data and prefetch aborts, as they both share the same mode. This adds 40 bytes of code. Change-Id: I5dd31930344ad4e3a658f8a9d366a87a300aeb67 Signed-off-by: Yann Gautier <yann.gautier@st.com>
* Merge "feat(rng-trap): add EL3 support for FEAT_RNG_TRAP" into integrationBipin Ravi2022-08-181-0/+11
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| * feat(rng-trap): add EL3 support for FEAT_RNG_TRAPJuan Pablo Conde2022-08-181-0/+11
| | | | | | | | | | | | | | | | | | | | | | FEAT_RNG_TRAP introduces support for EL3 trapping of reads of the RNDR and RNDRRS registers, which is enabled by setting the SCR_EL3.TRNDR bit. This patch adds a new build flag ENABLE_FEAT_RNG_TRAP that enables the feature. This feature is supported only in AArch64 state from Armv8.5 onwards. Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com> Change-Id: Ia9f17aef3444d3822bf03809036a1f668c9f2d89
* | feat(bl): add interface to query TF-A semantic verlaurenw-arm2022-08-021-0/+9
|/ | | | | | | | | Adding interface for stand-alone semantic version of TF-A for exporting to RSS attestation, and potentially other areas as well. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ib4a2c47aa1e42a3b850185e674c90708a05cda53
* Merge "feat(libfdt): add function to set MAC addresses" into integrationManish Pandey2022-07-081-0/+41
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| * feat(libfdt): add function to set MAC addressesAndre Przywara2022-04-261-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The devicetree specification[1] defines the generic DT properties "mac-address" and "local-mac-address", that allow to set the MAC address for a network device. This is needed because many platform network devices do not define a method for obtaining a unique MAC address, and many devices lack the non-volatile storage to hold such a number. Some platforms (for instance Allwinner) derive the MAC address from another unique SoC property, for instance some serial number. To allow those MAC address to be set by TF-A, add a function that finds the DT node of a network device (by using the "ethernet<x>" alias), then adding the "local-mac-address" property into that node, setting it to a user provided address. Platforms can use this function to generate MAC addresses in a platform specific way, and store them in the DT. DT consumers like U-Boot or the Linux kernel will automatically pick up the address from that property and program the MAC device accordingly. [1] https://devicetree-specification.readthedocs.io/en/latest/chapter4-device-bindings.html#local-mac-address-property Change-Id: I3f5766cc575fa9718f9ca23e8269b11495c43be2 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | feat(trbe): add trbe under feature detection mechanismJayanth Dodderi Chidanand2022-06-061-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds "FEAT_TRBE" to be part of feature detection mechanism. Previously feature enablement flags were of boolean type, containing either 0 or 1. With the introduction of feature detection procedure we now support three states for feature enablement build flags(0 to 2). Accordingly, "ENABLE_TRBE_FOR_NS" flag is now modified from boolean to numeric type to align with the feature detection. Change-Id: I53d3bc8dc2f6eac63feef22dfd627f3a48480afc Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
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