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* docs(prerequisites): update software and libraries prerequisitesGovindraj Raja2023-05-161-3/+3
| | | | | | | | | | | Update to use the following software: - mbed TLS == 3.4.0 - (DTC) >= 1.4.7 - Ubuntu 22.04 for builds. Signed-off-by: Govindraj Raja <govindraj.raja@arm.com> Change-Id: I384aab4dfee9cae9453eebf4091abe82ef9ccfaa
* Merge changes from topic "mp/feat_ras" into integrationManish Pandey2023-05-091-5/+4
|\ | | | | | | | | | | * changes: refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED refactor(ras): replace RAS_EXTENSION with FEAT_RAS
| * refactor(ras): replace RAS_EXTENSION with FEAT_RASManish Pandey2023-05-091-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current usage of RAS_EXTENSION in TF-A codebase is to cater for two things in TF-A : 1. Pull in necessary framework and platform hooks for Firmware first handling(FFH) of RAS errors. 2. Manage the FEAT_RAS extension when switching the worlds. FFH means that all the EAs from NS are trapped in EL3 first and signaled to NS world later after the first handling is done in firmware. There is an alternate way of handling RAS errors viz Kernel First handling(KFH). Tying FEAT_RAS to RAS_EXTENSION build flag was not correct as the feature is needed for proper handling KFH in as well. This patch breaks down the RAS_EXTENSION flag into a flag to denote the CPU architecture `ENABLE_FEAT_RAS` which is used in context management during world switch and another flag `RAS_FFH_SUPPORT` to pull in required framework and platform hooks for FFH. Proper support for KFH will be added in future patches. BREAKING CHANGE: The previous RAS_EXTENSION is now deprecated. The equivalent functionality can be achieved by the following 2 options: - ENABLE_FEAT_RAS - RAS_FFH_SUPPORT Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I1abb9ab6622b8f1b15712b12f17612804d48a6ec
* | Merge changes from topic "srm/Errata_ABI_El3" into integrationMadhukar Pappireddy2023-05-091-0/+7
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | * changes: docs(errata_abi): document the errata abi changes feat(fvp): enable errata management interface fix(cpus): workaround platforms non-arm interconnect refactor(errata_abi): factor in non-arm interconnect feat(errata_abi): errata management firmware interface
| * | docs(errata_abi): document the errata abi changesSona Mathew2023-05-051-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Updated errata ABI feature enable flag and the errata non-arm interconnect based flag, the default values for when the feature is not enabled. Change-Id: Ieb2144a1bc38f4ed684fda8280842a18964ba148 Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
* | | Merge changes from topic "bk/context_refactor" into integrationManish V Badarkhe2023-05-091-13/+11
|\ \ \ | |_|/ |/| | | | | | | | | | | * changes: fix(gicv3): restore scr_el3 after changing it refactor(cm): make SVE and SME build dependencies logical
| * | refactor(cm): make SVE and SME build dependencies logicalBoyan Karatotev2023-05-051-13/+11
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, enabling SME forces SVE off. However, the SME enablement requires SVE to be enabled, which is reflected in code. This is the opposite of what the build flags require. Further, the few platforms that enable SME also explicitly enable SVE. Their platform.mk runs after the defaults.mk file so this override never materializes. As a result, the override is only present on the commandline. Change it to something sensible where if SME is on then code can rely on SVE being on too. Do this with a check in the Makefile as it is the more widely used pattern. This maintains all valid use cases but subtly changes corner cases no one uses at the moment to require a slightly different combination of flags. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: If7ca3972ebc3c321e554533d7bc81af49c2472be
* | docs(build): update GCC to 12.2.Rel1 versionJayanth Dodderi Chidanand2023-05-091-1/+1
|/ | | | | | | | | | | | Updating toolchain to the latest production release version 12.2.Rel1 publicly available on https://developer.arm.com/ We build TF-A in CI using: AArch32 bare-metal target (arm-none-eabi) AArch64 ELF bare-metal target (aarch64-none-elf) Change-Id: Ib603cf7417e6878683a1100d5f55311188e36e8e Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* Merge "feat(el3-runtime): handle traps for IMPDEF registers accesses" into ↵Manish Pandey2023-05-021-0/+4
|\ | | | | | | integration
| * feat(el3-runtime): handle traps for IMPDEF registers accessesVarun Wadekar2023-04-301-0/+4
| | | | | | | | | | | | | | | | | | This patch introduces support to handle traps from lower ELs for IMPDEF system register accesses. The actual support is left to the platforms to implement. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I623d5c432b4ce4328b68f238c15b1c83df97c1e5
* | Merge "feat(sme): enable SME2 functionality for NS world" into integrationManish Pandey2023-04-281-0/+7
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| * | feat(sme): enable SME2 functionality for NS worldJayanth Dodderi Chidanand2023-04-271-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FEAT_SME2 is an extension of FEAT_SME and an optional feature from v9.2. Its an extension of SME, wherein it not only processes matrix operations efficiently, but also provides outer-product instructions to accelerate matrix operations. It affords instructions for multi-vector operations. Further, it adds an 512 bit architectural register ZT0. This patch implements all the changes introduced with FEAT_SME2 to ensure that the instructions are allowed to access ZT0 register from Non-secure lower exception levels. Additionally, it adds support to ensure FEAT_SME2 is aligned with the existing FEATURE DETECTION mechanism, and documented. Change-Id: Iee0f61943304a9cfc3db8f986047b1321d0a6463 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* | | Merge "docs: patch Poetry build instructions" into integrationJoanna Farley2023-04-262-37/+55
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| * | docs: patch Poetry build instructionsHarrison Mutai2023-04-252-37/+55
| |/ | | | | | | | | | | | | | | | | | | | | Some parts of the documentation referring to Poetry provides incorrect build instructions and has some minor formatting errors. Reformat the bits that require formatting, and fix the build instructions. These were originally part of the patch stack that added Poetry support but were accidentally reverted prior to merge. Signed-off-by: Harrison Mutai <harrison.mutai@arm.com> Change-Id: I336d3a7bbe99f75262430ae436f8ebc2cb050d2c
* | Merge "feat(gcs): support guarded control stack" into integrationBipin Ravi2023-04-251-0/+6
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| * feat(gcs): support guarded control stackMark Brown2023-04-181-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Arm v9.4 introduces support for Guarded Control Stack, providing mitigations against some forms of RPO attacks and an efficient mechanism for obtaining the current call stack without requiring a full stack unwind. Enable access to this feature for EL2 and below, context switching the newly added EL2 registers as appropriate. Change the FVP platform to default to handling this as a dynamic option so the right decision can be made by the code at runtime. Signed-off-by: Mark Brown <broonie@kernel.org> Change-Id: I691aa7c22e3547bb3abe98d96993baf18c5f0e7b
* | feat: add support for poetryHarrison Mutai2023-04-192-27/+32
|/ | | | | | | | | | | | | | | | | | New python dependencies are introduced by the memory mapping script. Rather than add another `requirements.txt` utilise poetry. This is a proper dependency management framework for Python. The two main upsides of using poetry instead of the traditional requirements.txt are maintainability and reproducibility. Poetry provides a proper lock file for pinning dependencies, similar to npm for JavaScript. This allows for separate environments (i.e. docs, tools) to be created efficiently, and in a reproducible manner, wherever the project is deployed. Having dependencies pinned in this manner is a boon as a security focused project. An additional upside is that we will receive security updates for dependencies via GitHub's Dependabot. Change-Id: I5a3c2003769b878a464c8feac0f789e5ecf8d56c Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
* feat(pie/por): support permission indirection and overlayMark Brown2023-04-121-0/+20
| | | | | | | | | | | | | | | | | | | Arm v8.9 introduces a series of features providing a new way to set memory permissions. Instead of directly encoding the permissions in the page tables the PTEs contain indexes into an array of permissions stored in system registers, allowing greater flexibility and density of encoding. Enable access to these features for EL2 and below, context switching the newly added EL2 registers as appropriate. Since all of FEAT_S[12]P[IO]E are separately discoverable we have separate build time options for enabling them, but note that there is overlap in the registers that they implement and the enable bit required for lower EL access. Change the FVP platform to default to handling them as dynamic options so the right decision can be made by the code at runtime. Signed-off-by: Mark Brown <broonie@kernel.org> Change-Id: Icf89e444e39e1af768739668b505661df18fb234
* Merge changes from topic "mb/rst-to-bl31-update" into integrationManish V Badarkhe2023-04-111-5/+0
|\ | | | | | | | | | | | | | | * changes: docs: update RESET_TO_BL31 documentation fix(bl31): avoid clearing of argument registers in RESET_TO_BL31 case Revert "docs(bl31): aarch64: RESET_TO_BL31_WITH_PARAMS" Revert "feat(bl31): aarch64: RESET_TO_BL31_WITH_PARAMS"
| * Revert "docs(bl31): aarch64: RESET_TO_BL31_WITH_PARAMS"Manish V Badarkhe2023-03-091-5/+0
| | | | | | | | | | | | | | | | | | Adopted RESET_TO_BL31_WITH_PARAMS functionality in RESET_TO_BL31 in the subsequent patches hence reverted this patch. This reverts commit ac4ac38c5443afdef38e38e9247c96359de3a2ea. Change-Id: I5fb8eaea47d0fd6d0171260c6d834ec8de588fad Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* | docs(porting): move porting guide upper in table of contentsSandrine Bailleux2023-04-112-3644/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The porting guide is currently hosted under the 'Getting started' section. Yet, porting the full firmware to a new platform is probably not the first thing that one would do. Before delving into the details, one would probably start by building the code for an emulated platform, such as Arm FVP. Furthermore, the porting guide is such a big and important document that it probably deserves being visible in the main table of contents. Thus, move it just above the list of supported platforms. Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: I51b3d2a93832505ab90d73c823f06f9540e84c77
* | docs(porting): remove reference to xlat_table lib v1Sandrine Bailleux2023-04-111-1/+1
| | | | | | | | | | | | | | | | Version 1 of the translation table library is deprecated. Refer to version 2 instead. Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: I10a4ab7b346ea963345f82baff2deda267c5308d
* | docs(porting): remove pull request terminologySandrine Bailleux2023-04-111-1/+1
| | | | | | | | | | | | | | | | | | The pull request terminology dates back from when TF-A repository was hosted on Github. Use a terminology that is more suited to Gerrit workflow. Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: Ieecf47617ca1cdb76b9c4a83f63ba3c402b9e975
* | docs(ethos-n): update porting-guide.rst for NPURob Hughes2023-04-041-3/+22
| | | | | | | | | | | | | | | | | | Add some missing configuration that must be done for supporting NPU on other platforms. Signed-off-by: Rob Hughes <robert.hughes@arm.com> Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: Ic505ea60f73b970d0d7ded101830eb2ce8c7ab64
* | feat(ethos-n): add separate RO and RW NSAIDsMikael Olsson2023-04-041-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | To be able to further restrict the memory access for the Arm(R) Ethos(TM)-N NPU, separate read-only and read/write NSAIDs for the non-protected and protected memory have been added to the Juno platform's TZMP1 TZC configuration for the NPU. The platform definition has been updated accordingly and the NPU driver will now only give read/write access to the streams that require it. Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I5a173500fc1943a5cd406a3b379e1f1f554eeda6
* | feat(ethos-n)!: load NPU firmware at BL2Rob Hughes2023-04-041-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BL2 on Juno now loads the Arm(R) Ethos(TM)-N NPU firmware into a fixed address, using the existing image loading framework. Includes support for TRUSTED_BOARD_BOOT, if enabled, using the firmware content and key certificates from the FIP. Supports the ARM_IO_IN_DTB option so can specify the firmware location from the dtb rather than it being hardcoded to the FIP Update makefile to automatically embed the appropriate images into the FIP. BREAKING CHANGE: Building the FIP when TZMP1 support is enabled in the NPU driver now requires a parameter to specify the NPU firmware file. Signed-off-by: Rob Hughes <robert.hughes@arm.com> Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I8cd64fb20d58f8bd539facb085606213d6cead06
* | feat(ethos-n): add support to set up NSAIDRajasekaran Kalidoss2023-04-041-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the TZC to allow the Arm(R) Ethos(TM)-N NPU to access the buffers allocated in a protected memory region, it must include the correct NSAID for that region in its transactions to the memory. This change updates the SiP service to configure the NSAIDs specified by a platform define. When doing a protected access the SiP service now configures the NSAIDs specified by the platform define. For unprotected access the NSAID is set to zero. Signed-off-by: Rajasekaran Kalidoss <rajasekaran.kalidoss@arm.com> Signed-off-by: Rob Hughes <robert.hughes@arm.com> Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I3360ef33705162aba5c67670386922420869e331
* | docs(sve): update defaults for FEAT_SVEJayanth Dodderi Chidanand2023-04-031-5/+6
| | | | | | | | | | | | | | | | | | | | FEAT_SVE build macro, "ENABLE_SVE_FOR_NS" default value has been updated to 2, to support its existing behavior of dynamic detection as well as keep it aligned with the changes concerning STATE=FEAT_STATE_CHECKED(2), part of Feature Detection procedure. Change-Id: Iee43e899f19dc9d5eb57c235998758f462a8c397 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* | feat(cpufeat): enable FEAT_SVE for FEAT_STATE_CHECKEDJayanth Dodderi Chidanand2023-03-281-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for runtime detection (ENABLE_SVE_FOR_NS=2), by splitting sve_supported() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we do SVE specific setup. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I1caaba2216e8e2a651452254944a003607503216 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* | feat(cpufeat): enable FEAT_SME for FEAT_STATE_CHECKEDJayanth Dodderi Chidanand2023-03-281-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for runtime detection (ENABLE_SME_FOR_NS=2), by splitting feat_sme_supported() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we do SME specific setup. Change the FVP platform default to the now supported dynamic option (=2),so the right decision can be made by the code at runtime. Change-Id: Ida9ccf737db5be20865b84f42b1f9587be0626ab Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* | Merge changes from topic "psci-osi" into integrationManish Pandey2023-03-282-0/+16
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: feat(sc7280): add support for PSCI_OS_INIT_MODE feat(fvp): enable support for PSCI OS-initiated mode feat(psci): update PSCI_FEATURES feat(psci): add support for OS-initiated mode feat(psci): add support for PSCI_SET_SUSPEND_MODE build(psci): add build option for OS-initiated mode docs(psci): add design proposal for OS-initiated mode
| * | feat(psci): add support for OS-initiated modeWing Li2023-03-201-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a `psci_validate_state_coordination` function that is called by `psci_cpu_suspend_start` in OS-initiated mode. This function validates the request per sections 4.2.3.2, 5.4.5, and 6.3 of the PSCI spec (DEN0022D.b): - The requested power states are consistent with the system's state - The calling core is the last running core at the requested power level This function differs from `psci_do_state_coordination` in that: - The `psci_req_local_pwr_states` map is not modified if the request were to be denied - The `state_info` argument is never modified since it contains the power states requested by the calling OS This is conditionally compiled into the build depending on the value of the `PSCI_OS_INIT_MODE` build option. Change-Id: I667041c842d2856e9d128c98db4d5ae4e4552df3 Signed-off-by: Wing Li <wingers@google.com>
| * | build(psci): add build option for OS-initiated modeWing Li2023-03-201-0/+3
| | | | | | | | | | | | | | | Change-Id: Ie4f7b6a36926ab075ebb9c6507a3ff48ce5538fe Signed-off-by: Wing Li <wingers@google.com>
* | | refactor(amu): unify ENABLE_AMU and ENABLE_FEAT_AMUv1Andre Przywara2023-03-271-12/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far we have the ENABLE_AMU build option to include AMU register handling code for enabling and context switch. There is also an ENABLE_FEAT_AMUv1 option, solely to protect the HAFGRTR_EL2 system register handling. The latter needs some alignment with the new feature scheme, but it conceptually overlaps with the ENABLE_AMU option. Since there is no real need for two separate options, unify both into a new ENABLE_FEAT_AMU name in a first step. This is mostly just renaming at this point, a subsequent patch will make use of the new feature handling scheme. Change-Id: I97d8a55bdee2ed1e1509fa9f2b09fd0bdd82736e Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | refactor(cpufeat): align FEAT_SB to new feature handlingAndre Przywara2023-03-221-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FEAT_SB introduces a new speculation barrier instruction, that is more lightweight than a "dsb; isb" combination. We use that in a hot path, so cannot afford and don't want a runtime detection mechanism. Nevertheless align the implementation of the feature detection part with the other features, but renaming the detection function, and updating the FEAT_DETECTION code. Also update the documentation. Change-Id: I2b86dfd1ad259c3bb99ab5186e2911ace454b54c Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKEDAndre Przywara2023-03-221-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support access to the trace unit by system registers (SYS_REG_TRACE) to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_SYS_REG_TRACE_FOR_NS=2), by adding is_feat_sys_reg_trace_supported(). That function considers both build time settings and runtime information (if needed), and is used before we access SYS_REG_TRACE related registers. The FVP platform decided to compile in support unconditionally (=1), even though this is an optional feature, so it is not available with the FVP model's default command line. Change that to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I450a574a4f6bd9fc269887037049c94c906f54b2 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | refactor(spe): enable FEAT_SPE for FEAT_STATE_CHECKEDAndre Przywara2023-03-201-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_SPE to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_SPE_FOR_NS=2), by splitting is_armv8_2_feat_spe_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access SPE related registers. Previously SPE was enabled unconditionally for all platforms, change this now to the runtime detection version. Change-Id: I830c094107ce6a398bf1f4aef7ffcb79d4f36552 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | refactor(cpufeat): rename ENABLE_SPE_FOR_LOWER_ELS to ENABLE_SPE_FOR_NSAndre Przywara2023-03-201-1/+1
|/ / | | | | | | | | | | | | | | | | | | | | | | At the moment we hardcode the SPE functionality to be available on the non-secure side only, by setting MDCR_EL2.E2PB accordingly. This should be reflected in the feature selection symbol, so rename that to ENABLE_SPE_FOR_NS, to make it clearer that SPE is not supported in the secure world. Change-Id: I3f9b48eab1a45d6ccfcbb9c90a11eeb66867ad9a Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | Merge "feat(tcr2): support FEAT_TCR2" into integrationManish Pandey2023-03-171-0/+7
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| * | feat(tcr2): support FEAT_TCR2Mark Brown2023-03-161-0/+7
| |/ | | | | | | | | | | | | | | | | | | | | | | Arm v8.9 introduces FEAT_TCR2, adding extended translation control registers. Support this, context switching TCR2_EL2 and disabling traps so lower ELs can access the new registers. Change the FVP platform to default to handling this as a dynamic option so the right decision can be made by the code at runtime. Signed-off-by: Mark Brown <broonie@kernel.org> Change-Id: I297452acd8646d58bac64fc15e05b06a543e5148
* | refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3Arvind Ram Prakash2023-03-151-7/+13
|/ | | | | | | | | | | | | | | | | | | BL2_AT_EL3 is an overloaded macro which has two uses: 1. When BL2 is entry point into TF-A(no BL1) 2. When BL2 is running at EL3 exception level These two scenarios are not exactly same even though first implicitly means second to be true. To distinguish between these two use cases we introduce new macros. BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2. Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where BL2 runs at EL3 (including four world systems). BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the repository. Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
* Merge "docs(drtm): mention DRTM_SUPPORT as an experimental build option" ↵Manish V Badarkhe2023-03-091-1/+1
|\ | | | | | | into integration
| * docs(drtm): mention DRTM_SUPPORT as an experimental build optionManish V Badarkhe2023-02-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | In spite of the fact that makefile [1] indicates that DRTM_SUPPORT is an experimental feature, it is better to mention the same in the documentation of the build option as well. [1]: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/Makefile#n897 Change-Id: Ibfa328ec8ed685ce715d144d979ba37e4f49f82e Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* | docs: discourage usage of weak functionsSandrine Bailleux2023-03-061-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | As a coding guideline, we now discourage introducing new weak functions in platform-agnostic code going forward and provide the rationale for this. This was already enforced most of the time in code reviews but this patch makes it explicit in the project's documentation. Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: I88f4a55788899fb4146c4d26afb3a7418376b30c
* | Merge changes from topic "panic_cleanup" into integrationBipin Ravi2023-02-231-6/+16
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | * changes: refactor(bl31): use elx_panic for sysreg_handler64 refactor(aarch64): rename do_panic and el3_panic refactor(aarch64): remove weak links to el3_panic refactor(aarch64): refactor usage of elx_panic refactor(aarch64): cleanup HANDLE_EA_EL3_FIRST_NS usage
| * | refactor(bl31): use elx_panic for sysreg_handler64Govindraj Raja2023-02-221-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we reach sysreg_handler64 from any trap handling we are entering this path from lower EL and thus we should be calling lower_el_panic reporting mechanism to print panic report. Make report_elx_panic available through assembly func elx_panic which could be used for reporting any lower_el_panic. Change-Id: Ieb260cf20ea327a59db84198b2c6a6bfc9ca9537 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
| * | refactor(aarch64): rename do_panic and el3_panicGovindraj Raja2023-02-211-6/+5
| |/ | | | | | | | | | | | | | | | | | | | | Current panic call invokes do_panic which calls el3_panic, but now panic handles only panic from EL3 anid clear separation to use lower_el_panic() which handles panic from lower ELs. So now we can remove do_panic and just call el3_panic for all panics. Change-Id: I739c69271b9fb15c1176050877a9b0c0394dc739 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
* | build: always prefix section names with `.`Chris Kay2023-02-201-7/+7
|/ | | | | | | | | | | | | | | | | Some of our specialized sections are not prefixed with the conventional period. The compiler uses input section names to derive certain other section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be difficult to select in linker scripts when there is a lack of a delimiter. This change introduces the period prefix to all specialized section names. BREAKING-CHANGE: All input and output linker section names have been prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`. Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c Signed-off-by: Chris Kay <chris.kay@arm.com>
* fix(docs): make required compiler version == rather than >=Boyan Karatotev2023-02-131-2/+8
| | | | | | | | | | TF-A carries its own compiler-rt so higher versions of the compilers may not necessarily work. Because TF-A is only tested on the specified versions in the CI, any breakage remains unknown. Update the prerequisites guide to make it more apparent that this is the case. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: Ia5da9c5ff505ead99f579f3f5fbe3a480d697c1d
* Merge changes from topic "bk/warnings" into integrationManish Pandey2023-01-102-1/+48
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: docs: describe the new warning levels build: add -Wunused-const-variable=2 to W=2 build: include -Wextra in generic builds docs(porting-guide): update a reference fix(st-usb): replace redundant checks with asserts fix(brcm): add braces around bodies of conditionals fix(renesas): align incompatible function pointers fix(zynqmp): remove redundant api_version check fix: remove old-style declarations fix: unify fallthrough annotations
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