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* fix(tree): correct some typosElyes Haouas2023-05-094-5/+5
| | | | | | | found using codespell (https://github.com/codespell-project/codespell). Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
* fix(renesas): align incompatible function pointersBoyan Karatotev2022-12-012-3/+3
| | | | | | | | | | | secure_boot_api_f is defined to take uint32_t, uint32_t, and void * parameters. However rom_secure_boot_api_f is defined to take uint32_t *, uint32_t *, void *. These are incompatible and cause a warning when compiling with -Wextra. Align the rom definition to the more generic definition from where it's called. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: Ia030803b3c2335d220aff09fc0eef5c7615276aa
* fix: unify fallthrough annotationsBoyan Karatotev2022-12-011-3/+2
| | | | | | | | | | | | | | | Compiling with -Wimplicit-fallthrough=3 (enabled by -Wextra) produces many warnings about fallthrough comments either missing or being wrong. Unify the comments so we comply with -Wextra. Note that Coverity recommends against using the __attribute__ directive. Also, zlib does not build with a higher value of -Wimplicit-fallthrough. Finally, compilers strip comments before expanding macros. As such, checkpatch's fallthrough annotation (or higher levels of the flag) isn't really possible. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I060cf4f8dc04c02cbb45cf4ceb69569a8369ccee
* feat(plat/rcar3): modify type for Internal function argumentTakuya Sakata2021-12-122-22/+22
| | | | | | | | | | | Modify the type of the variable that stores the value for MPIDR in the internal function from uint64_t to u_register_t. Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Ib5bda93d5432e0412132bddf41ead8ee3fcf9e46
* feat(plat/rcar3): modify sequence for update value for WUPMSKCA57/53Takuya Sakata2021-12-122-0/+26
| | | | | | | | | | | | | Add new function so that the value of bit at WUPMSKCA57/53, which points to CPU other than the BOOT CPU, is 1 at initialization. Modify sequence so that value of each bit for CPU at WUPMSKCA57/53 is basically 0 and target bit value is changed to 1 only when CPU_OFF. Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Id5dafc04e1dbaf265c8b67b903c335bb1af49914
* fix(plat/rcar3): fix to bit operation for WUPMSKCA57/53Takuya Sakata2021-12-121-3/+3
| | | | | | | | | | Change internal function to call when updating value for WUPMSKCA57/53. Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Id20e65e27861dd73a149ff487123859581a9b5c5
* fix(plat/rcar): change process that copy code to system ramToshiyuki Ogasahara2021-10-161-4/+4
| | | | | | | | | | | Change processing of invalidate instruction cache to after changing the RAM attribute. Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # squash with rcar_gen3: drivers: Disable data cache while Suspend To RAM Change-Id: I61339fc5415b26074b1e0753da4c4a432e8f83d9
* fix(plat/rcar): fix cache maintenance process of reading cert headerToshiyuki Ogasahara2021-10-161-7/+11
| | | | | | | | | Move calling inv_dcache_range from before io_read to after that. Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: Ic0dabf3eb94eeeb04099ed5127cdfda79bbac9b3
* fix(plat/rcar): fix to load image when option BL2_DCACHE_ENABLE is enabledToshiyuki Ogasahara2021-10-161-1/+2
| | | | | | | | | | | - Modify load destination variable of the Cert Header to static. - Modify the return value to error (IO_FAIL) when failed to check the Cert Header. Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: Ief09a841ec8d2ae236de82d04855e6a47cfb43f0
* feat(drivers/rcar3): add extra offset if booting B-sideMarek Vasut2021-09-121-0/+6
| | | | | | | | In case MFISBTSTSR bit 4 is 1, that means the loader was started as B-side. Load the remaining boot components from 8 MiB offset. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I11d882f30ca4f0cf55fd28d3470ff1063d350d10
* feat(plat/rcar3): modify SWDT counter setting for R-Car D3Toshiyuki Ogasahara2021-09-121-2/+4
| | | | | | | | | Modified the SWDT counter setting for R-Car D3. Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: If1fa12bf644486f3fad3c6b54cda6c4cbb604103
* feat(plat/rcar3): update DDR setting for R-Car D3Toshiyuki Ogasahara2021-09-121-19/+55
| | | | | | | | | Update R-Car D3 DDR setting rev.0.02. Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I3e3a202fbb0ff1f0f38a968ab5f8633604a46432
* feat(plat/rcar3): add process of SSCG setting for R-Car D3Toshiyuki Ogasahara2021-09-121-7/+19
| | | | | | | | | | | | - Added the condition where output the SSCG (MD12) setting to log for R-Car D3. - Added the process to switching the bit rate of SCIF by the SSCG (MD12) setting value for R-Car D3. Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: Iaf07fa4df12dc233af0b57569ee4fa9329f670a9
* feat(plat/rcar3): modify operation register from SYSCISR to SYSCISCRToshiyuki Ogasahara2021-09-121-1/+1
| | | | | | | | | | Modified the operation register to clearing the state bit of the SYSCISR register from SYSCISR to SYSCISCR. Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I9a0820b6414425fa2f4197f60852137827414a4d
* feat(plat/rcar3): add SYSCEXTMASK bit set/clear in scu_power_upToshiyuki Ogasahara2021-09-121-0/+22
| | | | | | | | | | Added the process of SYSECEXTMASK bit set/clear for following power Resume/Shutoff flow. Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I71ed22840a42e7ab7d87bfd4241eec6f5ddb129b
* fix(drivers/rcar3): console: fix a return value of console_rcar_initToshiyuki Ogasahara2021-09-121-2/+2
| | | | | | | | | This commit fixes a return value of console_rcar_init because it is expected to return 1 on success but the function always returns 0. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I97a6800578e3c517c0c1e3c00dc75f0ef75e8778
* feat(plat/rcar3): add new board revision for Salvator-XS/H3ULCBToshiyuki Ogasahara2021-07-101-3/+3
| | | | | | | | Add new board revision for 8GB 1rank of Salvator-XS/H3ULCB Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I9e0ef7340d92de9c892fc5bd04abe24ad6ee4286
* feat(drivers/rcar3): ddr: add function to judge a DDR rankToshiyuki Ogasahara2021-07-101-2/+43
| | | | | | | | | This commit adds the function to change the settings used for DDR initialization depending on the board ID and DDR rank. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I94d550cea620748f5b15499fed1b791a69d61592
* fix(drivers/rcar3): ddr: update DDR setting for H3, M3, M3NChiaki Fujii2021-07-102-3/+9
| | | | | | | | | [IPL/DDR] - Update H3, M3, M3N DDR setting rev.0.41. Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: Idd2fbea621365d84b566748b5b7d7fb2f0d08168
* fix(drivers/rcar3): i2c_dvfs: fix I2C operationToshiyuki Ogasahara2021-07-101-2/+2
| | | | | | | | | This commit fixes value to write to the ICCR register according to the hardware manual. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I1f612a482c012a6739e2f31db80224b222df766c
* fix(drivers/rcar3): fix CPG registers redefinitionToshiyuki Ogasahara2021-07-104-19/+10
| | | | | | | | This commit deletes the value of the redefined CPG register. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I05cf4a449ae28adb2ddd59593971a7d0cbcb21de
* fix(drivers/rcar3): emmc: remove CPG_CPGWPR redefinitionToshiyuki Ogasahara2021-07-102-4/+3
| | | | | | | | | emmc_registers.h contains redefinition of CPG_CPGWPR from bl2_cpg_register.h Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: Ie13590100df08f32193653e50191e66ed42d2b28
* renesas: rzg: Add support to identify EK874 RZ/G2E boardLad Prabhakar2021-04-202-1/+18
| | | | | | | | Add support to identify Silicon Linux RZ/G2E evaluation kit (EK874). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Id7bdbc9b0d25aa9af496d58d4bd5055579edc104
* drivers: renesas: common: watchdog: Add support for RZ/G2ELad Prabhakar2021-04-201-2/+2
| | | | | | | | Add watchdog support for RZ/G2E SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Ia813e051f6605028d0bb83967893ebd107fc8551
* drivers: renesas: rzg: Add QoS support for RZ/G2ELad Prabhakar2021-04-207-0/+690
| | | | | | | | Add QoS support for RZ/G2E SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I2c4373807ab8c550d86d6abc97f5b01f2fb78fb3
* drivers: renesas: rzg: Add PFC support for RZ/G2ELad Prabhakar2021-04-204-0/+738
| | | | | | | | Add pin control support for RZ/G2E SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I736724cc0dd32f2169018ed7f2f48319b039b61f
* drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoCLad Prabhakar2021-04-202-2/+2
| | | | | | | | | DRAM initialization on RZ/G2E SoC is identical to R-Car E3 so re-use the same. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I454fb40af4f8ce6c4c0d2a53edb307326efd02df
* renesas: rzg: Add support to identify HopeRun HiHope RZ/G2N boardLad Prabhakar2021-04-202-3/+13
| | | | | | | | Add support to identify HopeRun HiHope RZ/G2N board. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Ib47aba84b63488247f6e9da1f5878140129766ce
* drivers: renesas: common: emmc: Select eMMC channel for RZ/G2N SoCLad Prabhakar2021-04-201-4/+4
| | | | | | | | Select MMC_CH1 for eMMC on RZ/G2N SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Ib584b5203f38423ffe2ab52c6e6922f5b34a33ee
* drivers: renesas: rzg: Add QoS support for RZ/G2NLad Prabhakar2021-04-209-0/+1242
| | | | | | | | Add QoS support for RZ/G2N SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I663b50d9fb41b9b20a6b54795278659b2b184bc4
* drivers: renesas: rzg: Add PFC support for RZ/G2NLad Prabhakar2021-04-204-0/+1344
| | | | | | | | Add pin control support for RZ/G2N SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Ib5eb4f3b1b75e158ec13c4eefdbe9688344206a3
* drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoCLad Prabhakar2021-04-202-3/+37
| | | | | | | | Add support for initializing DRAM on RZ/G2N SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Id09a367b92b11a5da88f2dce6887677cc935d0c0
* renesas: rzg: Add support to identify HopeRun HiHope RZ/G2H boardLad Prabhakar2021-04-202-11/+20
| | | | | | | | Add support to identify HopeRun HiHope RZ/G2H board. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I6b28350ef50595fea9a1b1b7353fcabaeb935970
* drivers: renesas: common: emmc: Select eMMC channel for RZ/G2H SoCLad Prabhakar2021-04-201-4/+4
| | | | | | | | Select MMC_CH1 for eMMC on RZ/G2H SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I1bdfa462fd98b144042c014701b342b87e1efc9d
* drivers: renesas: rzg: Add QoS support for RZ/G2HLad Prabhakar2021-04-209-1/+1229
| | | | | | | | Add QoS support for RZ/G2H SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: If7d8940148fc31887568fd501c6cab609e715ba4
* drivers: renesas: rzg: Add PFC support for RZ/G2HLad Prabhakar2021-04-204-2/+1350
| | | | | | | | Add pin control support for RZ/G2H SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I06dc259d7d26a5a5313e8731ea72f846bfca09ed
* drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoCLad Prabhakar2021-04-202-2/+93
| | | | | | | | Add support for initializing DRAM on RZ/G2H SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Iae23f1093f65a9efd065d37b7d6e9340ff6350b9
* drivers: renesas: rzg: Switch using common ddr codeLad Prabhakar2021-04-2013-10493/+150
| | | | | | | | | Switch using common ddr driver code from renesas/common/ddr directory for RZ/G2M SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I807dcb0bc5186bd32bc1c577945d28634bb10e1f
* drivers: renesas: ddr: Move to commonLad Prabhakar2021-04-2021-37/+37
| | | | | | | | | Move ddr driver code to common directory, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I9aef73d3e9a027a127ce7483b72d339559866727
* renesas: rzg: emmc: Enable RZ/G2M supportBiju Das2021-01-131-4/+4
| | | | | | | | Enable eMMC driver support for RZ/G2M SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: I34803060c5b592ac24720b11d4a8cd3f9f40caee
* drivers: renesas: rzg: Add HiHope RZ/G2M board supportBiju Das2021-01-132-0/+94
| | | | | | | | Add support for HiHope RZ/G2M board. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: Ic8eed0729a42aeee94fc96d16b15b928232488a3
* renesas: rzg: Add PFC support for RZ/G2MBiju Das2021-01-134-0/+1404
| | | | | | | | Add pin control support for RZ/G2M SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: I08719015cab1ec59e2270523980a0a3e26e72c01
* renesas: rzg: Add QoS support for RZ/G2MBiju Das2021-01-1319-0/+2973
| | | | | | | | Add QoS support for RZ/G2M SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: If541278fd629761cc83398bba71e63f09d9dbee6
* renesas: rzg: Add support for DRAM initializationBiju Das2021-01-139-0/+10485
| | | | | | | | Add support for initializing DRAM on RZ/G2M SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: I99f1a6971a061a44687af498d55306a93e4fc8f7
* drivers: renesas: Move ddr/qos/qos header filesBiju Das2021-01-133-0/+0
| | | | | | | | | Move DDR/QoS/PFC header files, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: I2cc0ceda8d05b6b8d95a69afdc233dc0d098e850
* drivers: renesas: rpc: Move to commonBiju Das2021-01-132-0/+0
| | | | | | | | | Move rpc driver code to common directory, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: I04805d720d95b8edcc14e652f897fadc7f432197
* drivers: renesas: avs: Move to commonBiju Das2021-01-132-0/+0
| | | | | | | | | Move avs driver code to common directory, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: I85d9fa8b6abf158ce2521f1696478f7c5339fc42
* drivers: renesas: auth: Move to commonBiju Das2021-01-131-0/+0
| | | | | | | | | Move authentication driver code to common directory, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: I02592dfc714998bf89b9feaa78f685ae36be6f59
* drivers: renesas: dma: Move to commonBiju Das2021-01-131-0/+0
| | | | | | | | | Move dma driver code to common directory, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: Idce2e2f4e098cfc17219f963373d20ebf74e5b7c
* drivers: renesas: watchdog: Move to commonBiju Das2021-01-131-0/+0
| | | | | | | | | Move watch driver code to common directory, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: I235f2cde325a0feeadbfc4b7ee02e8b1186f7ea1
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