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| author | Xi Chen <xixi.chen@mediatek.corp-partner.google.com> | 2023-03-01 11:56:34 +0800 |
|---|---|---|
| committer | Xi Chen <xixi.chen@mediatek.corp-partner.google.com> | 2023-03-02 17:35:13 +0800 |
| commit | 65c8e9a26b25324b2f2239a25f82b5aef8b30029 (patch) | |
| tree | 227ccc3d7927f7297df47bbcc440bed4aabbc301 /cpu/intel/microcode/microcode2bin.sh | |
| parent | 1a4c51c8dc7400b3d2ca5c91e85a32086c866fc7 (diff) | |
| download | blobs-65c8e9a26b25324b2f2239a25f82b5aef8b30029.tar.gz | |
soc/mediatek/mt8188: Add scramble switch and fix 1RK register bit
This version adds scramble switch to support both production build and
serial build, and also fixes fast-k single rank wrong register bit.
BUG=b:269049451,b:267590318
TEST=Single rank DRAM suspend/resume pass, enable/disable scramble pass
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I7bf751e19d6df32bbd40b9dacad16fb99253d2ae
Diffstat (limited to 'cpu/intel/microcode/microcode2bin.sh')
0 files changed, 0 insertions, 0 deletions