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| author | Xi Chen <xixi.chen@mediatek.corp-partner.google.com> | 2023-03-01 11:56:34 +0800 |
|---|---|---|
| committer | Xi Chen <xixi.chen@mediatek.corp-partner.google.com> | 2023-03-02 17:35:13 +0800 |
| commit | 65c8e9a26b25324b2f2239a25f82b5aef8b30029 (patch) | |
| tree | 227ccc3d7927f7297df47bbcc440bed4aabbc301 /soc/mediatek/mt8188/dram.elf.md5 | |
| parent | 1a4c51c8dc7400b3d2ca5c91e85a32086c866fc7 (diff) | |
| download | blobs-65c8e9a26b25324b2f2239a25f82b5aef8b30029.tar.gz | |
soc/mediatek/mt8188: Add scramble switch and fix 1RK register bit
This version adds scramble switch to support both production build and
serial build, and also fixes fast-k single rank wrong register bit.
BUG=b:269049451,b:267590318
TEST=Single rank DRAM suspend/resume pass, enable/disable scramble pass
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I7bf751e19d6df32bbd40b9dacad16fb99253d2ae
Diffstat (limited to 'soc/mediatek/mt8188/dram.elf.md5')
| -rw-r--r-- | soc/mediatek/mt8188/dram.elf.md5 | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/soc/mediatek/mt8188/dram.elf.md5 b/soc/mediatek/mt8188/dram.elf.md5 index dc9d076..5c4b731 100644 --- a/soc/mediatek/mt8188/dram.elf.md5 +++ b/soc/mediatek/mt8188/dram.elf.md5 @@ -1 +1 @@ -2ab5d7370e14bae8c8199c7be9128d9e *dram.elf +2f1c79839e0a78d16c19b039d05a650a *dram.elf |