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* cpu/amd/model_10xx: Drop unused microcodeStefan Reinauer2020-11-118-1153/+0
| | | | | | | model_10xx was dropped from coreboot. No longer needed here. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I4ef565a6f3aa42e72ce12bf11d6e39b13b4b1697
* cpu/amd/model_fxx: Drop unused microcodeStefan Reinauer2020-11-115-443/+0
| | | | | | | model_fxx was dropped from coreboot. No longer needed here. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I439dae96cd9719ea982fbb3fca4bfe78e22566dc
* Drop geode_lxStefan Reinauer2020-11-10120-30386/+0
| | | | | | | | geode_lx has been dropped from coreboot a long time ago. Don't keep the blobs (and vsa code) around. It's all in the history. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I090a3eecada96b10933438f935539b7a25f4bfcb
* Remove execute permission from plaintext filesIdwer Vollering2020-10-17118-0/+0
| | | | | Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: Ibe3e69a546eb8bef334dac944016feefbf397d37
* Remove execute permission from all binariesAngel Pons2020-10-172-0/+0
| | | | | | | | These files aren't meant to be executed as-is. Most other binaries are not executable, so follow suit. Change-Id: I1eb433037d94af0d0b1539bea9347f503d023aa0 Signed-off-by: Angel Pons <th3fanbus@gmail.com>
* cpu/intel: Add STM SupportEugene D. Myers2019-12-173-0/+72
| | | | | | | | | | | | | | Binary STM file. Loaded by the "Add STM Support" changes into the MSEG stm.bin updated to PSTI7687 Note: this STM version has only been tested on a Minnowboard Max, Purism Librem 15v4, and a Sandybridge family CPU (Dell 990). README file added to meet the coreboot binary (blob) documentation requirements Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Change-Id: Ie1a5d1a5145dbf0c0e26c93f6ffd236d5aa79f77
* cpu/intel: Run microcode update scriptNico Huber2018-12-0633-101/+29
| | | | | | | | | `model_6xx` contained a microcode update for 660 so that's moved to `model_66x`. `model_406fx` vanished, but it wasn't hooked up in core- boot so remove it. Change-Id: I03af43776d1a71a3c2d39b30a256c9f8058bfda1 Signed-off-by: Nico Huber <nico.h@gmx.de>
* cpu/intel: Remove microcode header files, we use binaries nowNico Huber2018-12-06141-30039/+0
| | | | | | | If somebody misses them, they are in the history. Change-Id: I560f85ff6b215d7785ac5346c45f4992cd93c18b Signed-off-by: Nico Huber <nico.h@gmx.de>
* cpu/intel: remove microcode header files for model_306axMartin Kepplinger2018-07-062-869/+0
| | | | | | | | | | | | | | | | coreboot doesn't use the microcode header files anymore. The binaries are included, see src/cpu/intel/*/Makefile.inc. In the past, Intel has released its microcode updates in said header file format, has later released both the headers and binaries, and now releases the binaries only. Headers and the scripts that take them in order to generate binaries will become obsolete in the future. This removes the microcode header files for model_306ax so that they don't get out of sync when a new microcode update binary is included. Change-Id: I92bf7020cce3e36e1e6bd0068553647f0ff78dbf Signed-off-by: Martin Kepplinger <martink@posteo.de>
* cpu/amd/family_15h: Add latest AMD ucode filePaul Menzel2018-06-281-0/+0
| | | | | | | | | | | | | | | | | | Add the updated microcode update files from the Linux firmware repository [1]. Since the last upload, the commits below were added to the Linux firmware repository. * 5f8ca0c linux-firmware: Update AMD microcode patch firmware * 7710151 linux-firmware: Update AMD cpu microcode * 7518922 Update AMD cpu microcode for family 15h The current microcode patches should have features helping to mitigate the Spectre vulnerabilities. [1]: https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/amd-ucode Change-Id: I579abae1455a72007fc5931770b727e80b0b5b16 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
* cpu/intel: microcode: add license agreementMartin Kepplinger2018-05-141-0/+109
| | | | | | | | This adds the license Intel publishes these updates under. Source: https://downloadcenter.intel.com/download/27591 Change-Id: I4907aa59c3e9a82b9e3ce96cfe733b74e5a8d4b0 Signed-off-by: Martin Kepplinger <martink@posteo.de>
* cpu/intel: add microcode updates 20180312 for new CPU modelsMartin Kepplinger2018-04-1931-783/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel's microcode release 20180312 includes updates for many more CPU models than we currently track. By looking at what is included, we create the missing directories and run the update-microcode.sh and microcode2bin.sh scripts. This is the resulting change. Header files are left out because they are not used anymore. Sidenote: Since we create model_6ax, the relevant files from model_6xx move to model_6ax. Everything else is trivial addition. The available release notes for this and preceding releases follow quoted here: 20180312 Release == Updates upon 20171117 release == MODEL STEP f-mm-s:pf version -- New Platforms -- BDX-DE EGW A0 6-56-5:10 e000009 SKX B1 6-55-3:97 1000140 -- Updates -- SNB D2 6-2a-7:12 29->2d JKT C1 6-2d-6:6d 619->61c JKT C2 6-2d-7:6d 710->713 IVB E2 6-3a-9:12 1c->1f IVT C0 6-3e-4:ed 428->42c IVT D1 6-3e-7:ed 70d->713 HSW Cx/Dx 6-3c-3:32 22->24 HSW-ULT Cx/Dx 6-45-1:72 20->23 CRW Cx 6-46-1:32 17->19 HSX C0 6-3f-2:6f 3a->3c HSX-EX E0 6-3f-4:80 0f->11 BDW-U/Y E/F 6-3d-4:c0 25->2a BDW-H E/G 6-47-1:22 17->1d BDX-DE V0/V1 6-56-2:10 0f->15 BDW-DE V2 6-56-3:10 700000d->7000012 BDW-DE Y0 6-56-4:10 f00000a->f000011 SKL-U/Y D0 6-4e-3:c0 ba->c2 SKL R0 6-5e-3:36 ba->c2 KBL-U/Y H0 6-8e-9:c0 62->84 KBL B0 6-9e-9:2a 5e->84 CFL D0 6-8e-a:c0 70->84 CFL U0 6-9e-a:22 70->84 CFL B0 6-9e-b:02 72->84 SKX H0 6-55-4:b7 2000035->2000043 20171117 Release -- New Platforms -- CFL U0 (06-9e-0a:22) 70 CFL B0 (06-9e-0b:2) 72 SKX H0 (06-55-04:b7) 2000035 GLK B0 (06-7a-01:1) 1e APL Bx (06-5c-09:3) 2c -- Updates -- KBL Y0 (06-8e-0a:c0) 66->70 -- Removed files -- SKX H0 (06-55-04:97) 2000022 20170511 Release -- Updates -- BDX-ML B0/M0/R0 (06-4f-01:ef) b00001f->b000021 Skylake D0 (06-4e-03:c0) 9e->ba Broadwell ULT/ULX E/F-step (06-3d-04:c0) 24->25 ULT Cx/Dx (06-45-01:72) 1f->20 Crystalwell Cx (06-46-01:32) 16->17 Broadwell Halo E/G-step (06-47-01:22) 16->17 HSX EX E0 (06-3f-04:80) d->f Skylake R0 (06-5e-03:36) 9e->ba Haswell Cx/Dx (06-3c-03:32) 20->22 HSX C0 (06-3f-02:6f) 39->3a 20170707 Release -- New Platforms -- KBL H0 (06-8e-09:c0) 62 KBL Y0 (06-8e-0a:c0) 66 KBL B0 (06-9e-09:2a) 5e SKX H0 (06-55-04:97) 2000022 Change-Id: Idd9252eef3202d84504c690e7348377254a7185e Signed-off-by: Martin Kepplinger <martink@posteo.de>
* cpu/intel: apply microcode updates 20180312 to currently tracked modelsMartin Kepplinger2018-03-2717-4178/+4563
| | | | | | | | | | | | | | | This updates Intel's microcode updates for the CPU models we currently track to the latest release. These include meltdown/spectre mitigations. Source: https://downloadcenter.intel.com/download/27591 Applying the scripts results in changes to the models with CPU ID 206ax, 306ax, 306cx and 4065x. I tested this on a Thinkpad X230 (model 306ax). The revision is then 1f instead of 1b; (dmesg|grep microcode); loaded by coreboot (not Linux). Change-Id: Idf5aa85681391707822bbfe493cff269ff2b88eb Tested-by: Martin Kepplinger <martink@posteo.de> Signed-off-by: Martin Kepplinger <martink@posteo.de>
* nvidia/tegra132: Remove unused blobsMartin Roth2016-09-055-134/+0
| | | | | | | | | | The tegra 132 SOC support was removed from the coreboot codebase in commit 9ba06995 - soc/nvidia/tegra132: remove tegra132 support Remove the blobs since the chip is no longer used. Change-Id: Ic4ea493b2b5bb4e337ed617c647ad330b6b254ac Signed-off-by: Martin Roth <martinroth@chromium.org>
* qualcomm/ipq40xx: add more dummy filesPatrick Georgi2016-05-093-0/+2
| | | | | | | Again, these aren't the real thing. Change-Id: I0b51e7ee1a6f4e9b153c588ac9ef030226bba357 Signed-off-by: Patrick Georgi <pgeorgi@google.com>
* qualcomm/ipq40xx: Add placeholdersPatrick Georgi2016-05-094-0/+4
| | | | | | | | | These are dummy files. To build working images, you'll need to fetch the actual binaries from an existing image (or convince Qualcomm to give you the binaries). Change-Id: I89115b91bbe4c998c9b9854e6178e9788009b3a4 Signed-off-by: Patrick Georgi <pgeorgi@google.com>
* samsung/exynos5250: Add update-bl1.shStefan Reinauer2015-12-141-0/+26
| | | | | | | Moved from a lonely directory in the coreboot source tree Change-Id: I5312202d3068055e0297ddf5a9fa0672e9904c5a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Revert "Remove microcode stored in C-array format"Stefan Reinauer2015-11-27158-0/+33817
| | | | | | | | | | | | | | | This reverts commit 832bc6f1f8ffafc5ff397fd95616fdae988f224f. For compliance with our binary policy (*), and to be able to run the scripts producing the blobs without having to pull magic files from magic places, put these "source" files back in. (*) 2. Appropriate license (redistributable) a. The binary must be accompanied by a distribution license. [..] Change-Id: I99792dde209809ed8c90f5081593e38dc3b471b3 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* amd/model_10xxx: Upload latest AMD microcode files and remove unified blobTimothy Pearson2015-10-123-0/+0
| | | | | Change-Id: I80bdf5310801484f3ebf5b2343a69e780048bd0d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
* Remove microcode stored in C-array formatAlexandru Gagniuc2015-10-03158-33817/+0
| | | | | | | It's all binary now. Change-Id: I1dd897624b498e3707ac65f3cdcef7d857a1e6cf Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* cpu/amd/model_fxx: Store microcode in binary formatAlexandru Gagniuc2015-09-091-0/+0
| | | | | Change-Id: I1f7a67fd5801d96a70bf382cc8d76f3e121ea081 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* cpu/amd/model_10xxx: Store microcode in binary formatAlexandru Gagniuc2015-09-091-0/+0
| | | | | Change-Id: I0e8d675fcbd8fa281753fcc82543ec938d36dde7 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* cpu/via/nano: Store microcode in binary formatAlexandru Gagniuc2015-09-091-0/+0
| | | | | Change-Id: I7067e85d63f22de38d6f23430dd991698b15e763 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* via/nano: Move CPU microcode to 3rdparty/blobsStefan Reinauer2015-08-061-0/+921
| | | | | Change-Id: I71515a28dc6d330012f3e46312782e27db8e1c58 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* amd/model_fxx: Move CPU microcode to 3rdparty/blobsStefan Reinauer2015-08-064-0/+443
| | | | | Change-Id: Ic3164684d7aaf23d5db55218dc4a6d1c6131d5ea Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* amd/model_10xxx: Move CPU microcode to 3rdparty/blobsStefan Reinauer2015-08-068-0/+1153
| | | | | Change-Id: Ia8a441eef1cb67a367c6c8480d8acf7266e8c8f1 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Convert microcode to binaryStefan Reinauer2015-08-0622-0/+55
| | | | | | | | | | | | | | Intel's microcode is a binary that has been converted to an array of 32bit values. Instead of converting that back to binary on every compile, just store the microcode as a binary in the first place, and add that binary to CBFS. This patch adds a script that takes all current Intel microcode.h files and produces microcode.bin files. In addition, this patch also adds all the microcode.bin files produced by the script. Change-Id: Ia2712b50b49685f3eb781c0c68168ea1914350f8 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* ipq806x: trick mbncat into complianceStefan Reinauer2015-04-136-3/+3
| | | | | | | | | | | | | | | The fake binaries *.mbn need an 8 byte header d1 dc 4b 84 34 10 d7 73 for mbncat.py to accept them. Add all files that will be needed for IPQ806x builds down the line. This will still not produce a working coreboot binary, but it will fix compilation of coreboot. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I8cbb45eeb559f673deeefbf7692aff6b0211e59f
* ipq806x: Add dummy uber SBL binaryStefan Reinauer2015-04-102-0/+8
| | | | | | | | Please update uber-sbl.mbn from your existing coreboot image. These are only dummy images to make the build pass. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I20be2c7c71fcad274c7ef281f430f090b282e9ee
* nvidia/tegra132: Add CPU micorcode binariesMarc Jones2015-03-065-0/+134
| | | | | | | Add the Tegra 132 binaries from NVIDIA made available here: https://github.com/NVIDIA/cpu-microcode Signed-off-by: Marc Jones <marc.jones@se-eng.com>
* cpu/intel: Add haswell microcode (306cx and 4065x)Alexandru Gagniuc2015-02-044-0/+2697
| | | | | Change-Id: I084a2c6daee5a9cf0305758acd0ca8dff0a6beea Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* cpu/intel: Add model 306ax microcodeAlexandru Gagniuc2015-02-042-0/+805
| | | | | | | | This is done by creating a model_306ax dir. The update-microcodes script will then automatically extract the relevant microcode. Change-Id: Idf78088b58ad2ce9dc9e6881adf3a8ee9d2fd03c Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* cpu/intel: Add microcode files for supported CPUsAlexandru Gagniuc2015-02-04140-2/+27800
| | | | | | | | | | | | | Microcode files will need to be added to this repository before they can be removed from the main coreboot repo. Add them in anticipation of this change. The script was updated to pull the latest microcode. These files were extracted using the update-microcodes.sh script, and may not necessarily match the updates currently present in the main repository. Change-Id: I30d41ff31b1ebb6aaeb773c2c663d7176d27060d Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* update-microcodes.sh: Automatically generate include headersAlexandru Gagniuc2015-01-311-0/+7
| | | | | | | | | | | | | Rather than simply extracting the microcode updates, also create a microcode.h header for each model, to include the extracted microcode updates. This should make maintenance easier, as coreboot code will be able to simply include the "microcode.h" files in 3dparty rather than having to update the includes every time the microcodes are updated in here. Change-Id: I7abd81f984b1a61aeb6041d85b366e9a45c59421 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* qualcomm: Add IPQ8064 firmware placeholderMarc Jones2014-11-072-0/+8
| | | | | | | | | | | | | | ************************************************************************** * ATTENTION: The blobs/cpu/qualcomm/ipq8064/sbls.bin file is a * placeholder. * It is NOT a working IPQ8064 binary. * * Developers should maintain the IPQ8064 file on the flash device and be * sure to back it up prior to overwriting it with a coreboot image. ************************************************************************** Change-Id: Ifadede6d7851a7dfb2eada8f58752a5971f9a9aa Signed-off-by: Marc Jones <marc.jones@se-eng.com>
* AMD AGESA: Move Bald Eagle AGESA BLOB from CPU to new PI directoryBruce Griffith2014-07-282-312/+0
| | | | | | | | | Move the AGESA BLOB from the CPU directory to the PI directory to match the organization of the Steppe Eagle directory. Convert the license file from RTF to text so that it can be reviewed in Gerrit. Change-Id: I2b7e499ea458939af3ed5bf4e4e8d59301733ffc Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com>
* AMD AGESA: Add BLOBs to support AMD Embedded "Bald Eagle" processorsBruce Griffith2014-07-072-0/+312
| | | | | | | | | | | Add AGESA BLOB, VBIOS, and xHCI BLOB into the 3rdparty repo. These are explicitly to support AMD Embedded "Bald Eagle" processors in an FP3 package. These BLOBs may also work with other AMD Kaveri based processor but use with other Kaveris is not supported and has not been tested. Use at your own risk. Change-Id: Ia3807835fdde3b2ee76ab25cfa7943085866d794 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
* cpu/intel: Add microcode extractor script from main repoAlexandru Gagniuc2014-02-281-0/+107
| | | | | | | | | Add the update-microcodes.sh script in anticipation of removing the microcode updates from the main coreboot repository. The script is copied verbatim from main repository. Change-Id: I4d07d48646d71d58b5be329a24352ec04ae2f02d Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* exynos5420: add BL1 binaryStefan Reinauer2013-07-091-0/+0
| | | | | | | | This is a fake binary. Run strings on it to determine the URL of the real binary. Change-Id: Iaebdb2336e1df3b10395031b8f19d46b7550acc6 Signed-off-by: Stefan Reinauer <reinauer@google.com>
* exynos5250: change BL1 binary name to bl1.binStefan Reinauer2013-07-091-0/+0
| | | | | Change-Id: I5c092c74871b67a727c05064291d8d3f1a4a9654 Signed-off-by: Stefan Reinauer <reinauer@google.com>
* Add dummy bootblock for Exynos E5250Stefan Reinauer2013-01-041-0/+0
| | | | | | | | | Look into the file to find out where to get the actual bootblock for now. This is hopefully temporary to get the coreboot build process in place and working. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I53987a0515b00af83f959468296b4c5929ba49df
* Add Geode LX VSAPatrick Georgi2012-04-29120-0/+30386
license is proper, build environment not so, so distribute as binary.
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