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* pi/amd/00660F01/FP4/AGESA.bin: Remove execute file mode bitPaul Menzel2020-10-171-0/+0
| | | | | | | | It’s not an executable, so run `chmod -x AGESA.bin` to remove the execute file mode bit to be consistent with the other AGESA blobs. Change-Id: Ie5862c9937c1c14cca9171274df3e7bcca8dd04a Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
* 3rdparty/blobs/pi/amd/00670F00/FT4: Release AGESA.binRichard Spiegel2018-03-132-0/+42
| | | | | | | | | | | | | | | | | Some fixes and improvements happened in AGESA that need to be ported to coreboot. Among them we have: 1) A fix to AGESA_ALERT (only shows up after fixing AGESA_WARNING) 2) A fix to resetting at AmdInitPost after a 0x0CF9 reset with 0x0E 3) A call out by the AP to do CAR teardown externally Commit new AGESA FT4 binary. BUG=b:70338633 COMMIT=3313d277 TEST=These fixes and improvements were tested on kahlee and grunt boards before committing to Google's repository. Change-Id: I030eb0c30f68c30435906cff8b68bc3e0469ba95 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
* pi/amd/00670F00: Update AGESA to 1.3.0.9Marc Jones2018-02-014-0/+760
| | | | | | | | | | | | | | | Updates to 1.3.0.9 with the additional changes: Set BLDOPT_ALLOW_SPI_INTERFACE_UPDATE to FALSE Remove programming of WideIO0 Set FCH_NO_IR_SUPPORT for FT4 FAMILY15H_ST Fix SpreadSpectrum programming BUG:b:69807482 TEST=Build and boot Grunt Change-Id: I3de49438f72eadaddf40a0a2bf549c3404c7d1ff Signed-off-by: Marc Jones <marcj303@gmail.com>
* amd/pi/00670F00: Update AGESA.binMarc Jones2017-06-212-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | This update consists of two changes. Stoney: Enable Boottime Calibration The BTC feature is required for the SMU to correctly support AVFS. Without it, the SMU may send unsupportable VIDs to the regulator and cause the system to crash. Stoney: Remove SERIRQ setup Remove the SERIRQ setup in AGESA. It is platform specific and there isn't an AGESA API for changing the setting. In addition to not having an override, it was being set in amd_init_post, prior to memory setup, so prior to any possible interrupt handler. Finally it was setting quiet mode, which isn't supported by some LPC devices that can't recover, once switched to continiuos mode. A corresponding change to hudson lpc setup code in coreboot is required. Change-Id: I66bc60957af88ce4604de0b3727ef77891beadfb Signed-off-by: Marc Jones <marcj303@gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* pi/00670F00: Correct license fileMarshall Dawson2017-03-252-366/+404
| | | | | | | | Adjust the wording from a stale license agreement to a new and improved version from AMD. Change-Id: Id713a932ff0b253142315fd66f5f039f696c6ddc Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* pi/00670F00: Add FT4 AGESA.bin for Stoney platformMarshall Dawson2017-03-253-0/+1172
| | | | | | | | | | Add the FT4 version of the Stoney binary PI which corresponds to the same revision level as the FP4 one. This was built from commit c14ef54a. Change-Id: Ifb41e03ebf64b22ef0de6a9d12943cc9df9ee1f8 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit 6b23fa8d79b0bcfea94bc6b723aafa36bc26e477)
* pi/00670F00: Add AGESA.bin for Stoney platformMarshall Dawson2016-12-153-0/+1172
| | | | | | | | | | Add a custom build to support Family 15h Models 70h-7Fh. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry pick from e6e15473efa0a8870306745cac334b335778bc64) Change-Id: Icf20543a3625fde83f78adef47a5d0ef0244515a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* pi/amd: Fix AGESA.bin license filesMarshall Dawson2016-12-143-42/+42
| | | | | | | | | | | | | Replace non-ASCII characters with good values. These had consisted of formatted single and double quotes. No content of the license agreement is modified. This patch does not include the file for Stoney Ridge (00670F00) as that one contains new language from AMD. The three files here are identical and have been copied over time. Change-Id: I60b81bac0b5f3f8836871cc5c17e425aabc923e0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* AMD Merlin Falcon: Update to CarrizoPI 1.1.0.1 (Binary PI 1.5)WANG Siyuan2015-11-122-0/+6
| | | | | | | | | | Update AGESA.bin, PSP and VBIOS to CarrizoPI Version 1.1.0.1 Tested on Bettong rev C(DDR3) and rev F(DDR4). Both of the boards can boot to Windows 10. PCIe slots, USB and NIC work. Change-Id: Ie86bb0cf2e3cae7a9b446dfa93145ab2fce36c4f Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
* AMD Steppe Eagle: Update to MullinsPI 1.0.0.A (Binary PI 1.1)WANG Siyuan2015-08-252-1/+60
| | | | | | | | | | Update AGESA.bin and PSP to MullinsPI 1.0.0.A. This is tested on Olive Hill Plus. The board can boot to Windows 7. PCIe slot, USB and NIC work. Change-Id: I67817dc59f9984019ac66ce7a9ab1a2f34e0be9e Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
* AMD Merlin Falcon: Update to CarrizoPI 1.1.0.0 (Binary PI 1.4)WANG Siyuan2015-08-122-0/+7
| | | | | | | | | | Update AGESA.bin, PSP and VBIOS to CarrizoPI Version 1.1.0.0 Tested on Bettong rev C(DDR3) and rev F(DDR4). Both of the boards can boot to Windows 8.1. PCIe slots, USB and NIC work. Change-Id: Icb7a4f0724d9e18b22e8ffee13d19d20ddeb9dcb Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
* pi: Move AMD sources from blobs to vendorcodeMarc Jones2015-08-07104-56785/+0
| | | | | | | | | The AMD AGESA binaryPI sources were incorrectly committed to 3rdparty/blobs. Move them from blobs to vendorcode. Commit this after the files are committed to coreboot vendorcode/. Change-Id: If583c15ba4f7d63df264e09573c2605824836da0 Signed-off-by: Marc Jones <marc.jones@se-eng.com>
* AMD KaveriPI: add PlatformMemoryConfiguration.hWANG Siyuan2015-07-221-0/+515
| | | | | | | | | | This file is needed for memory configuration and was forgotten in Change I5e4b476 "northbridge/amd/pi: Add support for memory settings". So add it now. Change-Id: I0fb4cc8a2ba66e4d6f8cfc8ee00966ac6b94cade Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
* gcc-intrin.h: Drop __attribute__((optimize("Os")))Stefan Reinauer2015-07-071-61/+0
| | | | | | | | This attribute is not supported by clang, and will cause errors during compilation. Change-Id: Ia4bb030e8aae8eea7c271d912a6bfec167f54410 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* AMD Merlin Falcon: update binary PI to v1.3WANG Siyuan2015-07-072-0/+16
| | | | | | | | | | 1. Add NB PState support 2. Add FchSetSpi 3. Skip CF9 warm reset in FchInitResetHwAcpiP Change-Id: I0689bb835c29b83d947f609eaebfbe71eb54b3dd Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
* blobs: Fix assembler code to allow dropping -Wa,--divideStefan Reinauer2015-07-073-10/+10
| | | | | | | | Fix up all the code that is using / to use >> for divisions instead. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: If53096e5b840f39b4c499254207d05aacdf32acd
* AMD Steppe Eagle: add PlatformMemoryConfiguration.hWANG Siyuan2015-07-071-0/+516
| | | | | | Change-Id: Ib771dc6b637351cc2680fa63e0fa9f694eb96736 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
* AMD FT3b binary PI: Fix Windows 7 graphics driver hangWANG Siyuan2015-07-022-33/+10
| | | | | | | | | | | | | | | Windows 7 can't boot after the graphics driver is installed. The system hangs with a black screen screen as the OS loads. The problem was PSP initialization in AGESA PI. Two functions are added: PspMboxBiosCmdDramInfo and PspMboxBiosCmdExitBootServices This is the only change in this AGESA PI release. Tested on Olive Hill plus with graphics driver version 14.12. Change-Id: I7c413cd6506318d5a8fda5f1ab52a7168151affa Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
* AMD Merlin Falcon: remove build warningsWANG Siyuan2015-06-184-7/+15
| | | | | | | | | | | | | | | | | | | | 1. Add const in PCIe_COMPLEX_DESCRIPTOR and EarlyOemGpioTable The warnings are assignment discards 'const' qualifier in src/mainboard/amd/bettong/BiosCallOuts.c and src/mainboard/amd/bettong/PlatformGnbPcie.c 2. Change AltImageBasePtr and ImageBasePtr to VOID * AltImageBasePtr and ImageBasePtr are two fields in AMD_CONFIG_PARAMS. In orininal AGESA these two fiels are UINT32. This will result build warning in agesawrapper_amdinitpost: AmdParamStruct.StdHeader.AltImageBasePtr = NULL; So change these two according to Steppe Eagle and Bald Eagle. I also change the header files in binary PI code and rebuild AGESA.bin. The new AGESA.bin is the same as befor, so I didn't upload AGESA.bin. Change-Id: I59cf8b1bc0dc15c001f7b3ba0a5a945374663908 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
* AMD pi: replace LocateModule with agesawrapper_locate_moduleWANG Siyuan2015-06-151-58/+28
| | | | | | | | | Change pi/amd/00660F01/binaryPI/AGESA.c according to commit a710941e4: amd/pi: Move AGESA cbfs access function to coreboot Change-Id: I8c00b009a4939862a1ada912aaf850de81c133c6 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
* AMD PI: remove unuseful codeWANG Siyuan2015-06-151-166/+0
| | | | | | | | | AmdS3Save no longer exists in Carrizo. Imc lib should move to southbridge. Change-Id: I2c925adf4469bb53139abe48108800655db2a5fe Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
* pi/amd/00660F01/binaryPI/AGESA.c: remove printkWANG Siyuan2015-06-131-10/+0
| | | | | | Change-Id: I176784a8ab162244d9b9c36dc29a2956829341ed Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
* Porting.h: Don't define uintptr_tStefan Reinauer2015-06-132-2/+2
| | | | | | | | It's already defined in stdint.h and redefining it here conflicts with coreboot proper. Change-Id: I9a250b37b2f39278e4fdcd5c4b094457394549b6 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Add BLOBs to support AMD Embedded "Merlin Falcon" processorWANG Siyuan2015-06-0240-0/+20411
| | | | | | | | | | | | Add AGESA BLOB, head files, VBIOS, xHCI, IMC and PSP firmwares into the 3rdparty repo. These are explicitly to support AMD Embedded "Merlin Falcon" processors in a FP4 package. I have tested on board Bettong. Windows 7, Windows 8 and Ubuntu 14.04 can boot. Change-Id: I61abc61b0a837eb1e7b9bee6f6155f92d6c7419d Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
* amd/pi: Move AGESA cbfs access function to corebootMarc Jones2015-05-062-118/+68
| | | | | | | | | | The AGESA.c file in 3rdparty has cbfs access functions for locating the AGESA binaries. coreboot access functions need to be within coreboot where they can be updated with cbfs changes. Move the offending function to coreboot. Change-Id: Ic414d2c74e270548d5190e8c95e4cd7b8f3b8edd Signed-off-by: Marc Jones <marc.jones@se-eng.com>
* AGESA Version: Update Steppe Eagle to v1.0.0.4.0121William Wang2015-03-271-0/+0
| | | | | | | | | | | | | | | | | | | AGESA ENHANCEMENTS and FIXED BUGS after 1.0.0.4: - Fixed ECC issue - VRM values compatible with 53081 Rev. 1.03 Known Issues/Limitations: - Warm boot times may exceed cold boot times (affects ADK Fast Boot results) - fTPM and DASH are not yet fully implemented TEST: Boot win7/8,ubuntu OS on Olive Hill+ board successfully Verify that single ECC DIMM failure is gone Change-Id: I88b2c4bdeb6b638218a2d2935da6ad35a1f5dc0a Signed-off-by: William Wang <william.wang@amd.com> Signed-off-by: William Wang <william20140704@yahoo.com>
* AGESA Version: Upgrade 00630F01 (Bald Eagle) to v1.1.0.7Bruce Griffith2014-12-167-55/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Agesa ENHANCEMENTS and FIXED BUGS after 1.1.0.5: - BUG: Quad limited to Dual, XHCI controllers will disappear after r - ENH: FCH - POST API for GPIO definition - ENH: Reduce padding size for SMU firmware - BUG: Pcie Training Hangs on Broken Line failure - BUG: GNB IOAPIC devid in IVRS table should be 0:0:1 - ENH: Kaveri SMU Firmware 13.52.0 - BUG: Clear EcPortActive if IMC is disabled - BUG: Name string in Core 2 mismatch BSP setting - ENH: AGESA FCH USB EHCI Deep Blink Power Saving changes - BUG: eDP does not light up - BUG: BTS Shows warnings on several registers - ENH: KV Gen3 EQ CMOS Default Settings Changes - BUG: Wrong Timing parameters passed to PMU Message Block in mixed - ENH: Brand String Updates for Server and Embedded - ENH: Update NFC reference driver on KV as test result on KV platfo =========================================================================== Additional changes that are specific to coreboot: --------------------------------------------------------------------------- KaveriPI: Updates the IMC code to v1.1.2 Since existing Trinity/Richland and Ontario boards use the v1.1.1 code stored in southbridge/amd/hudson, move the Hudson v1.1.2 IMC binary from this update to KaveriPI under southbridge/amd/bolton. This is a potential problem for future KaveriPI updates since the path is changed from the AMD conventions used for KaveriPI. Technically, all discrete FCH designs (Kaveri, Trinity/Richland, Ontario, possibly Orochi) should use the latest Hudson IMC code. KavariPi: Change licensing on gcc-intrin.h per Palamida scan Palamida scan run on behalf of AMD found that the source license for gcc-intrin.h should be attributed to hackbunny@reactos.com. License was restored to the original KJK:Hyperion text. =========================================================================== Change-Id: Ie5ef48671ad4adab835ee6cba1dcafc4e12c18ee Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
* AGESA Version: Upgrade 00730F01 (Steppe Eagle) to v1.0.0.4Bruce Griffith2014-12-168-38/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Agesa ENHANCEMENTS and FIXED BUGS after 1.0.0.3: - ENH: FCH - POST API for GPIO definition - BUG: Pcie Training Hangs on Broken Line failure - ENH: Save Restore FakeSMI related registers for S3 - BUG: AGESA-FCH Can't set SPI Dual_122 mode - BUG: EHCI driven strength programming is not consistent with BKDG - BUG: D18F2x9C_x0D0F_0[F,8:0]04[POdtOff] fails to be maintained - ENH: PSP FW Stack (Mullins-Beema) version D.1.1.22 - ENH: Mullins_Firmware_14_31_0 - ENH: Sensor feature is not working - BUG: Potential Stack contaminate during TPM memory ready callback - ENH: ALIB skip training on hot unplug - ENH: PSP FW Stack (Mullins) version 0.1.1.1E - ENH: AGESA enhancement to implement workaround for ERRATA 793 Known Issues/Limitations - Warm boot times may exceed cold boot times (affects ADK Fast Boot results) - fTPM and DASH are not yet fully implemented ====================================================================== Additional changes that are specific to the AGESA binary for coreboot: ---------------------------------------------------------------------- MullinsPI: Change licensing on gcc-intrin.h per Palamida scan Palamida scan run on behalf of AMD found that the source license for gcc-intrin.h should be attributed to hackbunny@reactos.com. License was restored to the original KJK:Hyperion text. MullinsPI: Disable quad rank support Mullins does not support quad rank DIMMs. Turning this off allows both DIMMs to be detected on a olivehillplus. Mullins: GfxInitSview() needs to preserve GFX PCI config space The GfxInitSview() exits with the I/O decode disabled in the GFX (BDF=0:1.0) PCI config space. This commit copies the algorithm used for Trinity. MullinsPI: Prevent SPI Quad I/O mode from being used The AGESA code for SPI Quad I/O mode has multiple problems. These problems were first observed on the amd/DB-FT3b-LC board which has a SPI rom that supports quad I/O mode. In the function FchPlatformSpiQe() it is not able to correctly detect the QeEnabled bit to determine if quad mode should be turned on. This results in the function FchSetSpi() erasing the sector where the hudson/fwm header is stored and as a result the motherboard will not be able to be rebooted. MullinsPI: Turn on IOMMU The IOMMU cannot be turned on from coreboot if the IOMMU flag is set "OFF" in binary PI. This is because turning off IOMMU in build options disables compilation of the code that generates the IVRS ACPI table. Turning on the IOMMU flag should have no effect in coreboot code unless the IOMMU is explicitly enabled before the call to AMD_INIT_ENV. MullinsPI: Eliminate BOUNDS_CHK errors for HEAP locate objects function The HEAP locate objects function is frequently used in AGESA to test whether code has already run. This results in an AGESA BOUNDS_CHK error being reported and the subsequent logging of the error. These are not errors and they either cause a lot of work to revisit whether they are valid or all BOUNDS_CHK errors get ignored through invalid use of the error. Remove the reporting of BOUNDS_CHK errors within the HEAP locate buffer function. ====================================================================== Change-Id: Id45be29a330089e86a55bdd4571538fe43ea7668 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
* AMD 3rdparty PI: Make gcc-intrin.h match open-source AGESABruce Griffith2014-12-162-280/+336
| | | | | | | | Forward port commit: db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm Change-Id: I4a08ae9ed234aea671a8e6d83bfc352f3f422e4a Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
* AGESA binary PI: Add CONST to Azalia fields in callback structsBruce Griffith2014-11-222-6/+6
| | | | | | | | | | | | | | The Azalia table is a lookup. It is hard to imagine that it should not be CONST. The compiler does not complain when the Azalia related fields in the structs passed into the AGESA OEM callout are set CONST. If the compiler does not complain, then the calling function does not modify the Azalia lookup table. Therefore, there is no issue with setting the Azalia verb table pointer fields as CONST. All this does is provide more detail to the compiler so that it can flag errors at compile-time rather than runtime. Change-Id: I269c137f8644e97e095e1e39df1a255223cf07b0 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
* AGESA binary PI: Update the Bald Eagle binaryBruce Griffith2014-11-211-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | KavariPi: Change the default Sata6AhciCap to TRUE Change an internal AGESA variable to allow SATA AHCI mode to grab all six ports KaveriPI: Eliminate BOUNDS_CHK errors for HEAP locate objects function Internal to AGESA, HEAP locate functions return an error code. The error code shows up in the output from AmdReadEventLog(). Sometimes the locate functions are only used to determine if processing has already occurred. Change AGESA so that no error is generated in the log for simple locates. Memory allocates and deallocates still generate an error. Kaveri: GfxInitSview() needs to preserve GFX PCI config space When GfxInitSview() starts processing, it sets the I/O, memory, and busmaster bits in the integrated graphics device config space header. When GfxInitSview() completes the I/O bit is cleared. Change AGESA so that GfxInitSview() preserves the config space I/O, memory, and busmaster bits through the function. Change-Id: Ic30afefa9e0da14017642e1242976771908847bc Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
* AMD KaveriPI: Add PI header files to support binary AGESA releaseBruce Griffith2014-11-2137-0/+18771
| | | | | | | | Add the header files, Makefiles, and Kconfig files to support the AMD Embedded "Bald Eagle" binary AGESA. The header files need to exactly match the files used to build binary AGESA. Change-Id: I7a245bc4d36faa65838f3f41d2367889531d9aa7 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
* AMD AGESA: Move Bald Eagle BLOB to highlight only supports FP3 partsBruce Griffith2014-11-193-0/+0
| | | | | | | | | Move the Bald Eagle AGESA.bin file into a socket-specific directory to highlight that this BLOB is only for soldered down processors in an FP3 package. Change-Id: Iabef48c2f64a5d1fd7c1a9b1de65460308165f0c Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com>
* AMD MullinsPI: Add PI header files to support binary AGESA releaseBruce Griffith2014-08-2828-0/+17037
| | | | | | | | | Add the header files, Makefiles, and Kconfig files to support the AMD Embedded "Steppe Eagle" binary AGESA. The header files need to exactly the files used to build binary AGESA. Change-Id: Ia81caaaa3d90a3c23280a06fcfb50b922c94288a Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
* AMD AGESA: Move Steppe Eagle BLOB to highlight only supports FT3b partsBruce Griffith2014-08-283-0/+16
| | | | | | | | | Move the Steppe Eagle AGESA.bin file into a socket-specific directory to highlight that this BLOB is only for soldered down processors in an FT3b package. Change-Id: I291b6a60be7d8f9d784e75650bc721495d89a4c7 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
* AMD AGESA: Move Bald Eagle AGESA BLOB from CPU to new PI directoryBruce Griffith2014-07-283-0/+454
| | | | | | | | | Move the AGESA BLOB from the CPU directory to the PI directory to match the organization of the Steppe Eagle directory. Convert the license file from RTF to text so that it can be reviewed in Gerrit. Change-Id: I2b7e499ea458939af3ed5bf4e4e8d59301733ffc Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com>
* AMD AGESA: Add BLOBs to support AMD Embedded "Steppe Eagle" processorsBruce Griffith2014-07-283-0/+297
Add AGESA BLOB, VBIOS, and xHCI BLOB into the 3rdparty repo. These are explicitly to support AMD Embedded "Steppe Eagle" processors in an FT3b package. These BLOBs may also work with other AMD Mullins based processors but use with other variants is not supported. Change-Id: I6911e03fc605d38cf8283d34113ae8943ffa2500 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
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