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* soc/mediatek/mt8188: Add scramble switch and fix 1RK register bitXi Chen2023-03-023-1/+13
| | | | | | | | | | | This version adds scramble switch to support both production build and serial build, and also fixes fast-k single rank wrong register bit. BUG=b:269049451,b:267590318 TEST=Single rank DRAM suspend/resume pass, enable/disable scramble pass Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I7bf751e19d6df32bbd40b9dacad16fb99253d2ae
* soc/mediatek/mt8188: Add scramble switch for dpm version 0.2Xi Chen2023-02-225-2/+4
| | | | | | | | | | | In addition to DRAM, DPM also needs to handle scramble enable or disable. BUG=b:269049451 TEST=build pass and confirm enable/disable scramble successfully Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I291376edacfd4ae959764dbeb9b5b03739e3f4d5
* soc/mediatek/mt8188: Update MCUPM firmware from v1.01.03 to v1.01.04Jia-Wei Chang2022-12-233-1/+4
| | | | | | | | | | | | | | Update CPU DVFS OPP table to enhance power saving. The current CPU OPP voltage is conservative, so CPU OPP voltage can be further optimized for power saving. TEST=get "MediaTek MCUPM firmware: version 1.01.04" string by `strings mcupm.bin | grep -i media` TEST=boot to shell. BUG=NONE Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.corp-partner.google.com> Change-Id: I2dbb67f3b72f4fe7de2418189ae79f2e3694d9fa
* soc/mediatek/mt8186: Update SSPM firmware from v2.0.0 to v2.0.1Allen-KH Cheng2022-12-163-1/+4
| | | | | | | | | | | | | Fix the PMIC MT6315 id bug when registering the MT6315 regulator. BUG=b:249436110 TEST=Video playback works well on MT8186 and MT8186T Steelix after executing suspend_stress_test. TEST=get "MediaTek SSPM firmware: version 2.0.1" by strings sspm.bin | grep version Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Change-Id: Ib5d3612ac488aa41a9bcd61ad1e59048d395a3ef
* soc/mediatek/mt8186: Update SSPM firmware from v1.0.0 to v2.0.0Allen-KH Cheng2022-11-183-1/+4
| | | | | | | | | | Add PMIC MT6315 support for SSPM. BUG=b:249436110 TEST=test of suspend and resume pass. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Change-Id: I5cf5c0a46ce0af056dca6af7442a9ddb5be4b490
* soc/mediatek/mt8188: Update SSPM firmware from v1.88.00 to v1.88.01Liju-Clr Chen2022-11-143-1/+3
| | | | | | | | | | | | The last_emi is unsupported in ChromeOS project, so EMI driver would get a NULL address because no memory is reserved for last_emi. Add error checking for last_emi to avoid null pointer issue. BUG=b:233720142 TEST=Test of suspend resume passes. Change-Id: I7ceb048fc8e393607cab5096e6be626b9e0de135 Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
* soc/mediatek/mt8188: Update MCUPM firmware from v1.01.02 to v1.01.03Liju-Clr Chen2022-11-013-1/+5
| | | | | | | | | | | The efuse memory address is wrong for MCUPM to access. Add the offset to revise the efuse memory address. TEST=boot to shell. BUG=b:244250440 Change-Id: I6e1b873cffa2949997ff36346266446c9380ae04 Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
* soc/mediatek: Update capitalization of corebootMartin Roth2022-10-193-11/+11
| | | | | | | | | coreboot was spelled with a capital C in these files. We don't run the linters on these files, but since they're part of a coreboot-owned repo, let's fix them. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Icb1d6ee12057d552938496d198a17b6c8bfd93e8
* soc/mediatek/mt8188: Update MCUPM firmware from v1.01.01 to v1.01.02Liju-Clr Chen2022-09-203-1/+3
| | | | | | | | | | For ChromeOS project, we need to use MCUPM firmware without mtk header. TEST=boot to shell. BUG=b:244250440 Change-Id: I9730a9e16642644dd5282bb6714e29cf6f6ce335 Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
* soc/mediatek/mt8188: Update MCUPM firmware to v1.01.01Liju-Clr Chen2022-09-123-1/+4
| | | | | | | | | | | Revise the latency offset in SYSRAM for CPUFreq to be consistent with MT8195. TEST=boot to shell. BUG=b:244250440 Change-Id: Id2fee742b545d2b50595cf35baaf647008fd0e2e Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.corp-partner.google.com>
* soc/mediatek/mt8188: Add dram.elf version 0.1.0 for DRAM calibrationBo-Chen Chen2022-08-264-0/+116
| | | | | | | | | | This blob includes both full calibration and fast calibration flow. BUG=b:233720142 TEST=DRAM calibration pass Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I0a6c0085700cad4582de2d5b9c1a6a18e9313c35
* soc/mediatek/mt8188: Add SPM firmwareRex-BC Chen2022-08-234-0/+23
| | | | | | | | | | | | | Add SPM firmware version: pcm_suspend_20220705_v2_MP. SPM suspend can turn 26M clock off when system goes into suspend to save power. TEST=spm pc is 0x400 which is in idle state. BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I2221f757ebe29ba982b80291a3f2fbd314083615
* soc/mediatek/mt8188: Add dpm.pm and dpm.dm version 0.1Xi Chen2022-08-236-0/+37
| | | | | | | | | | Add dpm.pm and dpm.dm to support DRAM power management. TEST=build pass BUG=b:233720142 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I5d6d27c7d06b91a6530f9e259ae7bb69f1f12c60
* soc/mediatek/mt8188: Add SSPM firmware v1.88.00Rex-BC Chen2022-07-224-0/+27
| | | | | | | | | | Add sspm.bin to support suspend/resume. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ib10b9a9446ce7c057182e5ae0c087c4685db7f3f
* soc/mediatek/mt8188: Add MCUPM firmware v1.01.00Rex-BC Chen2022-07-224-0/+23
| | | | | | | | | | Add mcupm.bin initial version. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Idf21e2e79a02478621c09b02d068c6eed94beee5
* soc/mediatek/mt8188: Add MT8188 basic filesBo-Chen Chen2022-07-122-0/+12
| | | | | | | | | | Add README.md and license.txt. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ia5b394f463ed8c508bbe384383d8f3f6f1e2a523
* Revert "soc/mediatek/mt8186: Update SPM firmware to pcm_suspend_v0215_v10"Rex-BC Chen2022-03-283-4/+1
| | | | | | | | | | | | | | | | | This reverts commit d13ba18eb0daaa6d6cd708bb981ee0a562ac4789. Revert reason: CB:62327 was created to fix a suspend failure issue, where we disable 26M clock to bypass pmic wrap when suspending. However, it turns out that the root cause of the suspend issue is an incorrect pmif setting, which is fixed in CB:63089. Therefore, revert CB:62327 to enable 26M clock. BUG=b:215639203 TEST=test of suspend and resume pass. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I63923188b814f0b44690784b55bcec9aff9b3d23
* soc/mediatek/mt8195: Update dram.elf from 1.8.1 to 1.9.1Rex-BC Chen2022-03-073-1/+9
| | | | | | | | | | | Refactor dramc_param to share more structures (CB:61293). BUG=b:218577927 TEST=dram calibration pass Cq-Depend: chromium:3504704 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I05aac544fa3749c6d43dec2df034e1ebe265ebeb
* soc/mediatek/mt8186: Update SPM firmware to pcm_suspend_v0215_v10Jason-ch Chen2022-02-243-1/+4
| | | | | | | | | | | | The SRCLKENA0 is not pulled down when suspending. The root cause is that 26MHz clock is not disabled when suspending, so we update SPM firmware to fix this issue. TEST=verify 26MHz clock off using the oscilloscope. BUG=b:215639203 Signed-off-by: Jason-ch Chen <jason-ch.chen@mediatek.com> Change-Id: Iccaea858ff37cc3934c9a9a64bce7edf7cb0fbf1
* soc/mediatek/mt8195: Update dram.elf from 1.7.1 to 1.8.1Rex-BC Chen2022-02-093-1/+10
| | | | | | | | | | Move some structures to common folder (CB:61132). BUG=b:218577927 TEST=dram calibration pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If0e48b914fa951b4fc07ff1f25c4b4837131508a
* soc/mediatek/mt8186: Add dram.elf version 0.1.0 for DRAM calibrationRex-BC Chen2022-01-244-0/+111
| | | | | | | | | | | This blob includes both full calibration and fast calibration flow. TEST=DRAM calibration pass BUG=b:204226005 Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com> Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I010ded1cb68f4bd50f08927b0b4faaa9b9db67f6
* soc/mediatek/mt8186: List `sspm.bin` in READMERex-BC Chen2022-01-211-1/+2
| | | | | | | | TEST=build pass BUG=none Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I6fdd88e40a623e6268c685630a7987ba45efc66c
* soc/mediatek/mt8186: Add SSPM firmwareAllen-KH Cheng2021-12-244-0/+26
| | | | | | | | | | Add sspm.bin to support suspend/resume. TEST=build pass BUG=b:202871018 Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.corp-partner.google.com> Change-Id: Iae24878e1812c1e9e39ce8151c59e0ec2f234031
* soc/mediatek/mt8186: Add SPM firmwareRex-BC Chen2021-12-244-0/+23
| | | | | | | | | | | SPM suspend can turn 26M clock off when system goes into suspend to save power. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I5a35f1c10886d31da9ba6dfec5ee2b3cf0664563
* soc/mediatek/mt8186: Add MT8186 basic filesRex-BC Chen2021-11-162-0/+12
| | | | | | | Add README.md and license.txt. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ic6198353b1f7cca683875339a5fc4378a783d7a2
* soc/mediatek/mt8195: Update MCUPM firmware from v1.01.00 to v1.02.00Rex-BC Chen2021-10-063-1/+4
| | | | | | | | | | Changes: - Support CPU frequency for both 3.0G and 2.6G. BUG=b:201598555 TEST=boot to shell Change-Id: Ib4f93fda04836b6e41589ec82f80cd48cbcde13c
* soc/mediatek/mt8195: Add dpm.pm and dpm.dm version 1.0Ryan Chuang2021-07-296-0/+37
| | | | | | | See the README file for details. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I58f893fcee785c1f44cf176b4954964aa77a217a
* soc/mediatek/mt8195: Add dram.elf for full calibration flowRyan Chuang2021-07-224-0/+102
| | | | | Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com> Change-Id: I73e0b865bc018b6b67ab2ce67596e3fe98c48979
* soc/mediatek/mt8195: Update MCUPM firmware from v1.00.00 to v1.01.00Ben Tseng2021-07-223-1/+4
| | | | | | | | | | Update mcupm.bin version to v1.01.00. BUG=b:193000572 TEST=boot to shell Change-Id: Ib8da62875bedf5090ef458876c4bdd2503d6dc97 Signed-off-by: Ben Tseng <ben.tseng@mediatek.corp-partner.google.com>
* soc/mediatek/mt8195: Add SPM firmwareEdward-JW Yang2021-06-254-0/+23
| | | | | | | | SPM suspend can turn 26M clock off when system goes into suspend to save power. Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> Change-Id: If3ae0eb24f4990397e72d2acfa56a923cdd885e4
* soc/mediatek/mt8195: Add SSPM firmwareTinghan Shen2021-06-254-0/+30
| | | | | Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Change-Id: I2b21d1edc2498e8c75ef4ceb3c9683847a171f4a
* soc/mediatek/mt8195: Add MCUPM firmwareAlex Miao2021-06-254-0/+23
| | | | | | | Add mcupm.bin version v1.00.00. Signed-off-by: Alex Miao <alex.miao@mediatek.corp-partner.google.com> Change-Id: Id87cd5ce49b48de7ea45acc71462caa6d7dec61c
* soc/mediatek/mt8195: Add MT8195 basic filesRex-BC Chen2021-06-242-0/+12
| | | | | | | Add README.md and license.txt. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I7d3c036938b169191b8d14c2ce894230e099d5ce
* soc/mediatek/mt8192: Update MCUPM firmware from 1.00.06 to 1.00.07Andrew SH Cheng2021-05-314-2/+5
| | | | | | | | Changes from 1.00.06 to 1.00.07: - Add 2.6G CPU DVFS segment. Signed-off-by: Andrew SH Cheng <andrew-sh.cheng@mediatek.com> Change-Id: I4ecd0e816e7b12918470ac39afbded2105f8a4e7
* soc/mediatek/mt8192: Update DRAM blob to 1.6.3Yu-Ping Wu2021-05-114-2/+11
| | | | | | | | | | This fixes the auto reboot issue for Spherion. BUG=b:186363855 TEST=Hayato boots Change-Id: I143cb55cd63f5cc3b1820317c96aa3ef4af70f55 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
* soc/mediatek/mt8192: Update DRAM blob to 1.6.2Xi Chen2021-05-104-2/+13
| | | | | | | | | | This fixes memory training for DRAM Micron 8GB. BUG=b:186363844 TEST=Hayato boots Change-Id: I29f849bea76b4f5b0f1d8eac0b8c53c5cc3633ec Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
* soc/mediatek/mt8192: Update DRAM blob to 13869.0Yu-Ping Wu2021-04-094-5/+17
| | | | | | | | | | | | Update dram.elf from version 1.5.1 to 1.6.0, built from Chrome OS 13869.0.0. BUG=b:170687062 TEST=Hayato boots Cq-Depend: chromium:2783629, chromium:2783630 Change-Id: I13b63760448c1849ce73074bf1d0d6a118c336f8 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
* soc/mediatek/mt8183: Update DRAM calibration blob to 1.5.0Yu-Ping Wu2021-04-074-1/+17
| | | | | | | | | | | | | A new release of dram.elf built from Chrome OS 12573.224.0, which contains the version number string. BUG=b:173653085 TEST=emerge-kukui coreboot TEST=Krane boots BRANCH=kukui Change-Id: Ic113a6346cb57186efad77e36cc99ec957765b0e Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
* soc/mediatek/mt8183: Update DRAM calibration blob to 12573.197Hung-Te Lin2021-04-073-1/+9
| | | | | | | | | | | | A new release of dram.elf built from Chrome OS 12573.197.0, supporting 8GB byte mode. BUG=None BRANCH=kukui TEST=emerge-kukui coreboot chromeos-bootimage # boots properly Change-Id: Id445666d5f6a372f605eecf0f24b03ba1bf3efcc Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
* soc/mediatek/mt8183: Update DRAM calibration blob to 12573.136Hung-Te Lin2021-04-073-1/+8
| | | | | | | | | | | | | A new release of dram.elf built from Chrome OS 12573.136.0, improve 8GB stability. BUG=None BRANCH=kukui TEST=emerge-kukui coreboot chromeos-bootimage # boots properly Change-Id: Ie7baec46be614fb8bb942d49468de2d0ccd9e761 Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
* soc/mediatek/mt8183: Update DRAM calibration blob to 12573.132Hung-Te Lin2021-04-073-1/+9
| | | | | | | | | | | | | A new release of dram.elf built from Chrome OS 12573.132.0, supporting 6GB/4GB memory modules. BUG=None BRANCH=kukui TEST=emerge-kukui coreboot chromeos-bootimage # boots properly Change-Id: I4805e7c67cedfd90abe9f595487abe918f386011 Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
* soc/mediatek/mt8183: Update DRAM calibration blob to 12573.28Hung-Te Lin2021-04-073-1/+8
| | | | | | | | | | | | A new release of dram.elf built from Chrome OS 12573.28.0. BUG=b:80501386 BRANCH=kukui TEST=emerge-kukui coreboot chromeos-bootimage # boots properly Change-Id: I64987555f225a165d64003c1ccfb73da16c376b7 Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
* soc/mediatek/mt8183: Update DRAM calibration blob to 12573.25Hung-Te Lin2021-04-072-0/+7
| | | | | | | | | | | | A new release of dram.elf built from Chrome OS 12573.25.0. BUG=b:80501386 BRANCH=kukui TEST=emerge-kukui coreboot chromeos-bootimage # And boots properly Change-Id: Ia2d4571eb0a214989b31f87f3a6ecdcdc44cd37d Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
* soc/mediatek/mt8183: Update DRAM calibration blob to 12573.20Hung-Te Lin2021-04-073-1/+8
| | | | | | | | | | | | A new release of dram.elf built from Chrome OS 12573.20.0. BUG=b:80501386 BRANCH=kukui TEST=emerge-kukui coreboot chromeos-bootimage # And boots properly Change-Id: Idd889fd4383295a3568d63d7f6834bf52a7466d4 Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
* soc/mediatek/mt8183: Update DRAM full calibration blobHung-Te Lin2021-04-073-1/+9
| | | | | | | | | | | | | | A new release of dram.elf supporting dramc protocol version 2, built from Chrome OS 12573.16.0. BUG=b:80501386 BRANCH=kukui TEST=emerge-kukui coreboot chromeos-bootimage # And boots properly Change-Id: I7db6da9acc52855697de76b112baecbdf842588a Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
* soc/mediatek/mt8183: Add DRAM full calibration blobYu-Ping Wu2021-04-074-0/+118
| | | | | | | | | | | | | | | The dram.elf is added for mt8183 DRAM full calibration, which contains full calibrations for 3 frequencies: - 1600Mbps, 2400Mbps, 3200Mbps for discrete DDR, - 1600Mbps, 3200Mbps, 3600Mbps for eMCP DDR. BUG=b:80501386 BRANCH=kukui TEST=Full calibration runs successfully Change-Id: I5386af0e25878db40f013ef42df1f074426f13c2 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
* soc/mediatek/mt8192: Add EMI Settings of 8GB Normal ModeXi Chen2021-03-174-1/+20
| | | | | | | | | By default, 8GB DDRs may use byte mode, but some DDRs also use normal mode, add normal mode settings for supporting this kind of DDRs. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: Ia446c8d9279d815ff415af531a9bd872bded0515
* soc/mediatek/mt8192: Update MCUPM firmwareAndrew SH Cheng2021-03-174-2/+7
| | | | | | | | 1. Update mcupm.bin to v1.00.06 2. Modify SRAM layout for CPU DVFS Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com> Change-Id: Icfeb05de6a68379a17d6379e919c112dc8d8836f
* soc/mediatek/mt8192: Add version info for SSPMTinghan Shen2021-03-174-3/+8
| | | | | | | | 1. Label sspm.bin with version v1.0.0 2. disable boot log Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Change-Id: I23269e0ef69b988d10a467925111cc3e4ff76135
* soc/mediatek/mt8192: Support discrete DRAM modulesXi Chen2020-12-153-1/+9
| | | | | | | | | | | In additional to eMCP, some MT8192 devices may use discrete DRAM module and need a different calibration process. BUG=b:173653085 TEST=Stress pass Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: Ieddff1545de856f99c29cfe611bf6a5bd8deb0f3
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