diff options
| author | Gwendal Grignou <gwendal@chromium.org> | 2014-08-28 15:24:42 -0700 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-09-05 22:21:05 +0000 |
| commit | ad057248aee9a260725e531bd8f67e7a4eee65a6 (patch) | |
| tree | 72eedf8bf5cc3d6ea41caaf1b4da876cb333d8ec | |
| parent | 425d8a580467b9c9c74bfea68e78afbb87a7cf5e (diff) | |
| download | chrome-ec-ad057248aee9a260725e531bd8f67e7a4eee65a6.tar.gz | |
CHERRY-PICK: Ryu: Sensor hub changes for p1.
- Added LID_CLOSED_L and BASE_PRESET_L to PA2/PA3.
- Moved UART_TX/RX to PA9/PA10 (UART 1)
- Change DMA mapping to keep using DMA 4,5 for UART
BUG=chrome-os-partner:31527
TEST=None
BRANCH=ToT
Change-Id: Ie6138075bd901225b4fee48fc4ab4fa2add24b45
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215131
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit 1cf5ca93b63dc7d43dcc799bce4436ecaf1d4876)
Reviewed-on: https://chromium-review.googlesource.com/216762
| -rw-r--r-- | board/ryu_sh/board.c | 16 | ||||
| -rw-r--r-- | board/ryu_sh/board.h | 5 | ||||
| -rw-r--r-- | board/ryu_sh/gpio.inc | 8 |
3 files changed, 24 insertions, 5 deletions
diff --git a/board/ryu_sh/board.c b/board/ryu_sh/board.c index 577b5b3a0c..8a0ffe7968 100644 --- a/board/ryu_sh/board.c +++ b/board/ryu_sh/board.c @@ -30,3 +30,19 @@ const struct i2c_port_t i2c_ports[] = { }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); +void board_config_pre_init(void) +{ + /* + * enable SYSCFG clock: + * otherwise the SYSCFG peripheral is not clocked during the pre-init + * and the register write as no effect. + */ + STM32_RCC_APB2ENR |= 1 << 0; + /* + * Remap USART DMA to match the USART driver + * the DMA mapping is : + * Chan 4 : USART1_TX + * Chan 5 : USART1_RX + */ + STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10);/* Remap USART1 RX/TX DMA */ +} diff --git a/board/ryu_sh/board.h b/board/ryu_sh/board.h index 298f0df223..fa30c89760 100644 --- a/board/ryu_sh/board.h +++ b/board/ryu_sh/board.h @@ -11,9 +11,9 @@ /* 48 MHz SYSCLK clock frequency */ #define CPU_CLOCK 48000000 -/* the UART console is on USART2 (PA2/PA3) */ +/* the UART console is on USART1 (PA9/PA10) */ #undef CONFIG_UART_CONSOLE -#define CONFIG_UART_CONSOLE 2 +#define CONFIG_UART_CONSOLE 1 /* By default, enable all console messages */ #define CC_DEFAULT CC_ALL @@ -21,6 +21,7 @@ /* Optional features */ #define CONFIG_STM_HWTIMER32 #define CONFIG_I2C +#define CONFIG_BOARD_PRE_INIT #undef CONFIG_LID_SWITCH #define CONFIG_VBOOT_HASH #undef CONFIG_WATCHDOG_HELP diff --git a/board/ryu_sh/gpio.inc b/board/ryu_sh/gpio.inc index f2adefb4b5..c1f4357910 100644 --- a/board/ryu_sh/gpio.inc +++ b/board/ryu_sh/gpio.inc @@ -18,13 +18,15 @@ GPIO(SH_EC_SIGNAL, A, 7, GPIO_OUT_LOW, NULL) GPIO(SH_IRQ_L, A, 11, GPIO_OUT_LOW, NULL) /* Inputs */ +GPIO(LID_CLOSED, A, 2, GPIO_INPUT, NULL) +GPIO(BASE_PRESENT, A, 3, GPIO_INPUT, NULL) GPIO(COMPASS_DRDY, B, 11, GPIO_INPUT, NULL) GPIO(AP_IN_SUSPEND, B, 15, GPIO_INPUT, NULL) #if 0 /* Alternate functions */ -GPIO(UART_TX, A, 2, GPIO_OUT_LOW, NULL) -GPIO(UART_RX, A, 3, GPIO_OUT_LOW, NULL) +GPIO(UART_TX, A, 9, GPIO_OUT_LOW, NULL) +GPIO(UART_RX, A, 10, GPIO_OUT_LOW, NULL) #endif /* Needed to bypass flash write protection */ @@ -40,6 +42,6 @@ GPIO(SLAVE_I2C_SDA, B, 7, GPIO_INPUT, NULL) GPIO(MASTER_I2C_SCL, B, 13, GPIO_INPUT, NULL) GPIO(MASTER_I2C_SDA, B, 14, GPIO_INPUT, NULL) -ALTERNATE(A, 0x000C, 1, MODULE_UART, 0) /* USART2: PA2/PA3 */ +ALTERNATE(A, 0x0600, 1, MODULE_UART, 0) /* USART1: PA9/PA10 */ ALTERNATE(B, 0x00C0, 1, MODULE_I2C, 0) /* I2C SLAVE:PB6/7 */ ALTERNATE(B, 0x6000, 5, MODULE_I2C, 0) /* I2C MASTER:PB13/14 */ |