diff options
| author | Jeff Chase <jnchase@google.com> | 2020-06-02 21:23:47 -0400 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-06-15 20:07:54 +0000 |
| commit | 7ef17b2fd86720624b37482a28360008554c5fca (patch) | |
| tree | 86f2e12cb80013258a8aa9aba1d5fa3589ab6ff5 | |
| parent | f680d5e119c0561b33abe350243ff9aa37237788 (diff) | |
| download | chrome-ec-7ef17b2fd86720624b37482a28360008554c5fca.tar.gz | |
endeavour: gpios: USB-C polarity and PSE reset
The polarity gpio is used to detect the USB-C plug orientation since
Endeavour does not have a PD controller. This will be read using
ectool by the factory test.
The PSE controller reset signal was moved from PLTRST to an EC gpio
output. Not currently used since we reset using an I2C register.
BUG=b:157236750, b:156399232
TEST=ectool gpioget USB_C0_POL_L, EC_RST_LTC4291_L
BRANCH=none
Change-Id: Ic6abec17654b8d30486f6e4bbb23f70b11d18e43
Signed-off-by: Jeff Chase <jnchase@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2241183
Reviewed-by: Joe Tessler <jrt@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
(cherry picked from commit 6bf64c105990fb33b6ffdbb603ca0dff8f4085a6)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2246946
| -rw-r--r-- | board/endeavour/gpio.inc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/board/endeavour/gpio.inc b/board/endeavour/gpio.inc index fb09aa03ed..2f8b1a8fa4 100644 --- a/board/endeavour/gpio.inc +++ b/board/endeavour/gpio.inc @@ -25,6 +25,7 @@ GPIO(POE_LTC_PGOOD, PIN(C, 5), GPIO_INPUT) /* PoE power good */ GPIO(PSE_PWM_INT, PIN(3, 7), GPIO_INPUT) /* PoE LTC interrupt */ GPIO(V3P3A_I350_PG, PIN(4, 4), GPIO_INPUT) /* Disconnected */ GPIO(USB_C0_VBUS_DET_L, PIN(9, 7), GPIO_INPUT) /* USB-C VBUS */ +GPIO(USB_C0_POL_L, PIN(C, 2), GPIO_INPUT) /* USB-C Polarity */ GPIO(PCH_RTCRST, PIN(E, 7), GPIO_OUT_LOW) /* RTCRST# to SOC */ GPIO(WLAN_OFF_L, PIN(7, 2), GPIO_OUT_LOW) /* Disable WLAN */ @@ -41,6 +42,7 @@ GPIO(CCD_MODE_ODL, PIN(6, 3), GPIO_INPUT) /* Case Closed Debug Mode */ GPIO(EC_HAVEN_RESET_ODL, PIN(0, 2), GPIO_ODR_HIGH) /* H1 Reset */ GPIO(ENTERING_RW, PIN(7, 6), GPIO_OUTPUT) /* EC Entering RW */ GPIO(PMIC_INT_L, PIN(6, 0), GPIO_INPUT) /* PMIC interrupt */ +GPIO(EC_RST_LTC4291_L, PIN(9, 4), GPIO_OUT_HIGH) /* PSE controller reset */ GPIO(POWER_RATE, PIN(7, 1), GPIO_INPUT) /* High: i3/5/7. Low: Celeron */ GPIO(PP3300_USB_PD_EN, PIN(6, 7), GPIO_OUT_HIGH) /* Initialize PP3300_USB_PD_EN as output high */ @@ -75,7 +77,6 @@ GPIO(PP3300_TPU_EN, PIN(0, 1), GPIO_OUT_HIGH) /* TPU 3.3V enable */ GPIO(USB_C0_CHARGE_L, PIN(C, 0), GPIO_OUT_LOW) /* C0 Charge enable */ GPIO(AC_JACK_CHARGE_L, PIN(C, 3), GPIO_OUT_LOW) /* AC jack charge enable */ GPIO(USB_C0_PD_RST_ODL, PIN(0, 3), GPIO_OUT_LOW) /* C0 PD Reset */ -GPIO(USB_C0_DP_HPD, PIN(9, 4), GPIO_INPUT) /* C0 DP Hotplug Detect */ GPIO(USB_C0_TCPC_PWR, PIN(8, 4), GPIO_OUT_LOW) /* Enable C0 TCPC Power */ GPIO(TYPE_C_60W, PIN(3, 3), GPIO_OUTPUT | GPIO_PULL_DOWN) GPIO(TYPE_C_65W, PIN(3, 4), GPIO_OUTPUT | GPIO_PULL_DOWN) |