diff options
author | Mulin Chao <mlchao@nuvoton.com> | 2018-06-28 19:35:32 -0700 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2018-07-15 21:49:10 -0700 |
commit | 47de1e86750736f6e410e359b8f5980811be3556 (patch) | |
tree | c562ec6b967a7bbfe5b1037152d73bf243bd4a61 | |
parent | 0a3f63f67aea7da6df6df2040f8c3647a1510ece (diff) | |
download | chrome-ec-47de1e86750736f6e410e359b8f5980811be3556.tar.gz |
npcx7: system: change the default value of FMUL_WIN_DLY
This CL changes the default value of Nuvoton internal register,
FMUL_WIN_DLY, from 0x8A to 0x81 on npcx7 ec series. It increases the tuning rate
of the FMULs to improve audio quality. For consistency, this is done across all
NPCX7 devices.
BRANCH=none
BUG=b:74600211
TEST=make buildall; Run cold-reset stress test over 3 days on grunt. No symptoms
occurred.
Change-Id: I5ad0c115da4254413d43269140eb71092c11b3b2
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1134815
Reviewed-by: Jett Rink <jettrink@chromium.org>
-rw-r--r-- | chip/npcx/registers.h | 1 | ||||
-rw-r--r-- | chip/npcx/system.c | 8 |
2 files changed, 9 insertions, 0 deletions
diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index 94c34f34f6..be5f236a5b 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -889,6 +889,7 @@ enum { (NPCX_PMC_BASE_ADDR + 0x024)) #define NPCX_PWDWN_CTL(offset) REG8(NPCX_PWDWN_CTL_ADDR(offset)) #if defined(CHIP_FAMILY_NPCX7) +#define NPCX_FMUL_WIN_DLY REG8(NPCX_PMC_BASE_ADDR + 0x010) #define NPCX_RAM_PD(offset) REG8(NPCX_PMC_BASE_ADDR + 0x020 + offset) #endif diff --git a/chip/npcx/system.c b/chip/npcx/system.c index c3cace0fb9..c6440134ad 100644 --- a/chip/npcx/system.c +++ b/chip/npcx/system.c @@ -722,6 +722,14 @@ void system_pre_init(void) */ system_mpu_config(); + /* + * Change FMUL_WIN_DLY from 0x8A to 0x81 for better WoV + * audio quality. + */ +#ifdef CHIP_FAMILY_NPCX7 + NPCX_FMUL_WIN_DLY = 0x81; +#endif + #ifdef CONFIG_CHIP_PANIC_BACKUP chip_panic_data_restore(); #endif |