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| author | Furquan Shaikh <furquan@google.com> | 2018-02-19 17:30:43 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-02-20 22:50:02 -0800 |
| commit | 78a407f0a15d1bfc7fa098751e292bc7e7b190a3 (patch) | |
| tree | 73ef4edc41d2a3bc8291af2994cef19dde662f0b | |
| parent | fac65e668c2b02d0af419c6a48f33a44f8e4ba11 (diff) | |
| download | chrome-ec-78a407f0a15d1bfc7fa098751e292bc7e7b190a3.tar.gz | |
npcx: Set ESPI_MAXFREQ based on FMCLK value
According to NPCX data sheets (NPCX5 and NPCX7), ESPI_MAXFREQ should
be decided based on the value of FMCLK. Since we are setting FMCLK to
30MHz on NPCX5, eSPI_MAXFREQ needs to be set to 33MHz.
This change sets ESPI_MAXFREQ_MAX depending upon the value of FMCLK.
BUG=b:73504527
BRANCH=fizz?
TEST=Verified that on soraka ESPI_MAXFREQ is set to 33MHz. Also, ran
some reboot tests to ensure that there is no regression in boot time.
Change-Id: Iaee89078741cf44c7ac232e2ee14d75384f68a35
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/925843
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
| -rw-r--r-- | chip/npcx/registers.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index d451eb04c9..9bca32e82f 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -9,6 +9,8 @@ #define __CROS_EC_REGISTERS_H #include "common.h" +#include "clock_chip.h" + /******************************************************************************/ /* * Macro Functions @@ -1673,9 +1675,23 @@ enum { }; #if defined(CHIP_FAMILY_NPCX5) + +#if (FMCLK <= 33000000) +#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_33 +#elif (FMCLK <= 48000000) +#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50 +#else #define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_66 +#endif + #elif defined(CHIP_FAMILY_NPCX7) + +#if (FMCLK <= 33000000) +#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_33 +#else #define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50 +#endif + #else #error "Please define NPCX_ESPI_MAXFREQ_MAX for your chip." #endif |