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| author | Ruibin Chang <Ruibin.Chang@ite.com.tw> | 2018-08-16 18:28:56 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-08-23 13:21:01 -0700 |
| commit | 599232ba9103d3b8a0df0f24792801b6734ded64 (patch) | |
| tree | 623724006f64ab604ec3e3163854818d13bee5f0 | |
| parent | fa2d1dd956c0235b46be93361890485b1e3acc32 (diff) | |
| download | chrome-ec-599232ba9103d3b8a0df0f24792801b6734ded64.tar.gz | |
tcpm:it83xx: GRL-USB-PD TDA2.1.2.1 BMC test
According to BMC signaling scheme of PD3.0 spec,
we should set different Rx threshold in SRC and SNK role
for well performance of receiving data. So we add these
settings and can pass GRL-USB-PD compliance TDA2.1.2.1
test item.
BUG=none
BRANCH=none
TEST=GRL-USB-PD compliance test.
Change-Id: Ie4fccaa362a83462e57237ed4f0cbe5683da2fea
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1170721
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
| -rw-r--r-- | driver/tcpm/it83xx.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/driver/tcpm/it83xx.c b/driver/tcpm/it83xx.c index 72e27ad6b4..b959eb6c89 100644 --- a/driver/tcpm/it83xx.c +++ b/driver/tcpm/it83xx.c @@ -280,6 +280,17 @@ static void it83xx_set_power_role(enum usbpd_port port, int power_role) { /* PD_ROLE_SINK 0, PD_ROLE_SOURCE 1 */ if (power_role == PD_ROLE_SOURCE) { + /* + * bit[2,3] BMC Rx threshold setting + * 00b: power neutral + * 01b: sinking power => + * High to low Y3Rx threshold = 0.38, + * Low to high Y3Rx threshold = 0.54. + * 10b: sourcing power => + * High to low Y3Rx threshold = 0.64, + * Low to high Y3Rx threshold = 0.79. + */ + IT83XX_USBPD_CCADCR(port) = 0x08; /* bit0: source */ SET_MASK(IT83XX_USBPD_PDMSR(port), (1 << 0)); /* bit1: CC1 select Rp */ @@ -287,6 +298,17 @@ static void it83xx_set_power_role(enum usbpd_port port, int power_role) /* bit3: CC2 select Rp */ SET_MASK(IT83XX_USBPD_BMCSR(port), (1 << 3)); } else { + /* + * bit[2,3] BMC Rx threshold setting + * 00b: power neutral + * 01b: sinking power => + * High to low Y3Rx threshold = 0.38, + * Low to high Y3Rx threshold = 0.54 + * 10b: sourcing power => + * High to low Y3Rx threshold = 0.64, + * Low to high Y3Rx threshold = 0.79 + */ + IT83XX_USBPD_CCADCR(port) = 0x04; /* bit0: sink */ CLEAR_MASK(IT83XX_USBPD_PDMSR(port), (1 << 0)); /* bit1: CC1 select Rd */ |