endeavour: initial build from kalista/karmastabilize-12669.B

BUG=b:143780700
TEST=emerge-endeavour chromeos-ec

Change-Id: Ib2cec6df3ab6a89a1b7bb278f231cb6b6da4f3ce
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893543
Tested-by: Jeff Chase <jnchase@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Jeff Chase <jnchase@google.com>
Auto-Submit: Jeff Chase <jnchase@google.com>

8 files changed, 1512 insertions, 0 deletions

diff --git a/board/endeavour/board.c b/board/endeavour/board.c
new file mode 100644
index 0000000000..5a28a926e8
--- /dev/null
+++ b/board/endeavour/board.c
@@ -0,0 +1,545 @@
+/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Endeavour board configuration */
+
+#include "adc.h"
+#include "adc_chip.h"
+#include "battery.h"
+#include "bd99992gw.h"
+#include "board_config.h"
+#include "button.h"
+#include "chipset.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "driver/pmic_tps650x30.h"
+#include "driver/temp_sensor/tmp432.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/tcpm/tcpm.h"
+#include "espi.h"
+#include "extpower.h"
+#include "espi.h"
+#include "fan.h"
+#include "fan_chip.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "math_util.h"
+#include "oz554.h"
+#include "pi3usb9281.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "spi.h"
+#include "switch.h"
+#include "system.h"
+#include "task.h"
+#include "temp_sensor.h"
+#include "timer.h"
+#include "uart.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+
+static uint8_t board_version;
+static uint32_t oem;
+static uint32_t sku;
+
+enum bj_adapter {
+	BJ_90W_19V,
+	BJ_135W_19V,
+};
+
+/*
+ * Bit masks to map SKU ID to BJ adapter wattage. 1:135W 0:90W
+ * KBL-R i7 8550U	4	135
+ * KBL-R i5 8250U	5	135
+ * KBL-R i3 8130U	6	135
+ * KBL-U i7 7600	3	135
+ * KBL-U i5 7500	2	135
+ * KBL-U i3 7100	1	90
+ * KBL-U Celeron 3965	7	90
+ * KBL-U Celeron 3865	0	90
+ */
+#define BJ_ADAPTER_135W_MASK (1 << 4 | 1 << 5 | 1 << 6 | 1 << 3 | 1 << 2)
+
+static void tcpc_alert_event(enum gpio_signal signal)
+{
+	if (!gpio_get_level(GPIO_USB_C0_PD_RST_ODL))
+		return;
+#ifdef HAS_TASK_PDCMD
+	/* Exchange status with TCPCs */
+	host_command_pd_send_status(PD_CHARGE_NO_CHANGE);
+#endif
+}
+
+void vbus0_evt(enum gpio_signal signal)
+{
+	task_wake(TASK_ID_PD_C0);
+}
+
+#include "gpio_list.h"
+
+/* Hibernate wake configuration */
+const enum gpio_signal hibernate_wake_pins[] = {
+	GPIO_POWER_BUTTON_L,
+};
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	/* Vbus sensing (1/10 voltage divider). */
+	[ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* TODO: Verify fan control and mft */
+const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_FAN_PWR_EN,
+};
+
+const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2180,
+	.rpm_start = 2180,
+	.rpm_max = 4900,
+};
+
+const struct fan_t fans[] = {
+	[FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
+};
+BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
+
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+const struct i2c_port_t i2c_ports[]  = {
+	{"tcpc", I2C_PORT_TCPC0, 400, GPIO_I2C0_0_SCL, GPIO_I2C0_0_SDA},
+	{"eeprom", I2C_PORT_EEPROM, 400, GPIO_I2C0_1_SCL, GPIO_I2C0_1_SDA},
+	{"backlight", I2C_PORT_BACKLIGHT, 100, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
+	{"pmic", I2C_PORT_PMIC, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
+	{"thermal", I2C_PORT_THERMAL, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/* TCPC mux configuration */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	/* Alert is active-low, push-pull */
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC0,
+			.addr_flags = I2C_ADDR_TCPC0_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+	},
+};
+
+static int ps8751_tune_mux(int port)
+{
+	/* 0x98 sets lower EQ of DP port (4.5db) */
+	mux_write(port, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98);
+	return EC_SUCCESS;
+}
+
+struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.driver = &tcpci_tcpm_usb_mux_driver,
+		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.board_init = &ps8751_tune_mux,
+	}
+};
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_USB1_ENABLE,
+	GPIO_USB2_ENABLE,
+	GPIO_USB3_ENABLE,
+	GPIO_USB4_ENABLE,
+};
+
+void board_reset_pd_mcu(void)
+{
+	gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 0);
+	msleep(1);
+	gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 1);
+}
+
+void board_tcpc_init(void)
+{
+	int port, reg;
+
+	/* This needs to be executed only once per boot. It could be run by RO
+	 * if we boot in recovery mode. It could be run by RW if we boot in
+	 * normal or dev mode. Note EFS makes RO jump to RW before HOOK_INIT. */
+	board_reset_pd_mcu();
+
+	/*
+	 * Wake up PS8751. If PS8751 remains in low power mode after sysjump,
+	 * TCPM_INIT will fail due to not able to access PS8751.
+	 * Note PS8751 A3 will wake on any I2C access.
+	 */
+	i2c_read8(I2C_PORT_TCPC0, I2C_ADDR_TCPC0_FLAGS, 0xA0, &reg);
+
+	/* Enable TCPC interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
+
+	/*
+	 * Initialize HPD to low; after sysjump SOC needs to see
+	 * HPD pulse to enable video path
+	 */
+	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++) {
+		const struct usb_mux *mux = &usb_muxes[port];
+		mux->hpd_update(port, 0, 0);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL) &&
+			gpio_get_level(GPIO_USB_C0_PD_RST_ODL))
+		return PD_STATUS_TCPC_ALERT_0;
+	return 0;
+}
+
+/*
+ * TMP431 has one local and one remote sensor.
+ *
+ * Temperature sensors data; must be in same order as enum temp_sensor_id.
+ * Sensor index and name must match those present in coreboot:
+ *     src/mainboard/google/${board}/acpi/dptf.asl
+ */
+const struct temp_sensor_t temp_sensors[] = {
+	{"TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+			TMP432_IDX_LOCAL, 4},
+	{"TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+			TMP432_IDX_REMOTE1, 4},
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * Thermal limits for each temp sensor.  All temps are in degrees K.  Must be in
+ * same order as enum temp_sensor_id.  To always ignore any temp, use 0.
+ */
+struct ec_thermal_config thermal_params[] = {
+	/* {Twarn, Thigh, Thalt}, <on>
+	 * {Twarn, Thigh, X    }, <off>
+	 * fan_off, fan_max
+	 */
+	{{0, C_TO_K(80), C_TO_K(81)}, {0, C_TO_K(78), 0},
+		C_TO_K(4), C_TO_K(76)},	/* TMP431_Internal */
+	{{0, 0, 0}, {0, 0, 0}, 0, 0},	/* TMP431_Sensor_1 */
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
+
+/* Initialize PMIC */
+#define I2C_PMIC_READ(reg, data) \
+	i2c_read8(I2C_PORT_PMIC, TPS650X30_I2C_ADDR1_FLAGS, (reg), (data))
+
+#define I2C_PMIC_WRITE(reg, data) \
+	i2c_write8(I2C_PORT_PMIC, TPS650X30_I2C_ADDR1_FLAGS, (reg), (data))
+
+static void board_pmic_init(void)
+{
+	int err;
+	int error_count = 0;
+	static uint8_t pmic_initialized = 0;
+
+	if (pmic_initialized)
+		return;
+
+	/* Read vendor ID */
+	while (1) {
+		int data;
+		err = I2C_PMIC_READ(TPS650X30_REG_VENDORID, &data);
+		if (!err && data == TPS650X30_VENDOR_ID)
+			break;
+		else if (error_count > 5)
+			goto pmic_error;
+		error_count++;
+	}
+
+	/*
+	 * VCCIOCNT register setting
+	 * [6] : CSDECAYEN
+	 * otherbits: default
+	 */
+	err = I2C_PMIC_WRITE(TPS650X30_REG_VCCIOCNT, 0x4A);
+	if (err)
+		goto pmic_error;
+
+	/*
+	 * VRMODECTRL:
+	 * [4] : VCCIOLPM clear
+	 * otherbits: default
+	 */
+	err = I2C_PMIC_WRITE(TPS650X30_REG_VRMODECTRL, 0x2F);
+	if (err)
+		goto pmic_error;
+
+	/*
+	 * PGMASK1 : Exclude VCCIO from Power Good Tree
+	 * [7] : MVCCIOPG clear
+	 * otherbits: default
+	 */
+	err = I2C_PMIC_WRITE(TPS650X30_REG_PGMASK1, 0x80);
+	if (err)
+		goto pmic_error;
+
+	/*
+	 * PWFAULT_MASK1 Register settings
+	 * [7] : 1b V4 Power Fault Masked
+	 * [4] : 1b V7 Power Fault Masked
+	 * [2] : 1b V9 Power Fault Masked
+	 * [0] : 1b V13 Power Fault Masked
+	 */
+	err = I2C_PMIC_WRITE(TPS650X30_REG_PWFAULT_MASK1, 0x95);
+	if (err)
+		goto pmic_error;
+
+	/*
+	 * Discharge control 4 register configuration
+	 * [7:6] : 00b Reserved
+	 * [5:4] : 01b V3.3S discharge resistance (V6S), 100 Ohm
+	 * [3:2] : 01b V18S discharge resistance (V8S), 100 Ohm
+	 * [1:0] : 01b V100S discharge resistance (V11S), 100 Ohm
+	 */
+	err = I2C_PMIC_WRITE(TPS650X30_REG_DISCHCNT4, 0x15);
+	if (err)
+		goto pmic_error;
+
+	/*
+	 * Discharge control 3 register configuration
+	 * [7:6] : 01b V1.8U_2.5U discharge resistance (V9), 100 Ohm
+	 * [5:4] : 01b V1.2U discharge resistance (V10), 100 Ohm
+	 * [3:2] : 01b V100A discharge resistance (V11), 100 Ohm
+	 * [1:0] : 01b V085A discharge resistance (V12), 100 Ohm
+	 */
+	err = I2C_PMIC_WRITE(TPS650X30_REG_DISCHCNT3, 0x55);
+	if (err)
+		goto pmic_error;
+
+	/*
+	 * Discharge control 2 register configuration
+	 * [7:6] : 01b V5ADS3 discharge resistance (V5), 100 Ohm
+	 * [5:4] : 01b V33A_DSW discharge resistance (V6), 100 Ohm
+	 * [3:2] : 01b V33PCH discharge resistance (V7), 100 Ohm
+	 * [1:0] : 01b V18A discharge resistance (V8), 100 Ohm
+	 */
+	err = I2C_PMIC_WRITE(TPS650X30_REG_DISCHCNT2, 0x55);
+	if (err)
+		goto pmic_error;
+
+	/*
+	 * Discharge control 1 register configuration
+	 * [7:2] : 00b Reserved
+	 * [1:0] : 01b VCCIO discharge resistance (V4), 100 Ohm
+	 */
+	err = I2C_PMIC_WRITE(TPS650X30_REG_DISCHCNT1, 0x01);
+	if (err)
+		goto pmic_error;
+
+	/*
+	 * Increase Voltage
+	 *  [7:0] : 0x2a default
+	 *  [5:4] : 10b default
+	 *  [5:4] : 01b 5.1V (0x1a)
+	 */
+	err = I2C_PMIC_WRITE(TPS650X30_REG_V5ADS3CNT, 0x1a);
+	if (err)
+		goto pmic_error;
+
+	/*
+	 * PBCONFIG Register configuration
+	 *   [7] :      1b Power button debounce, 0ms (no debounce)
+	 *   [6] :      0b Power button reset timer logic, no action (default)
+	 * [5:0] : 011111b Force an Emergency reset time, 31s (default)
+	 */
+	err = I2C_PMIC_WRITE(TPS650X30_REG_PBCONFIG, 0x9F);
+	if (err)
+		goto pmic_error;
+
+	/*
+	 * V3.3A_DSW (VR3) control. Default: 0x2A.
+	 * [7:6] : 00b Disabled
+	 * [5:4] : 00b Vnom + 3%. (default: 10b 0%)
+	 */
+	err = I2C_PMIC_WRITE(TPS650X30_REG_V33ADSWCNT, 0x0A);
+	if (err)
+		goto pmic_error;
+
+	CPRINTS("PMIC init done");
+	pmic_initialized = 1;
+	return;
+
+pmic_error:
+	CPRINTS("PMIC init failed");
+}
+
+void chipset_pre_init_callback(void)
+{
+	board_pmic_init();
+}
+
+/**
+ * Notify PCH of the AC presence.
+ */
+static void board_extpower(void)
+{
+	gpio_set_level(GPIO_PCH_ACPRESENT, extpower_is_present());
+}
+DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
+
+enum battery_present battery_is_present(void)
+{
+	return BP_NO;
+}
+
+int64_t get_time_dsw_pwrok(void)
+{
+	/* DSW_PWROK is turned on before EC was powered. */
+	return -20 * MSEC;
+}
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED_RED]  = { 3, PWM_CONFIG_DSLEEP, 100 },
+	[PWM_CH_LED_BLUE] = { 5, PWM_CONFIG_DSLEEP, 100 },
+	[PWM_CH_FAN] = {4, PWM_CONFIG_OPEN_DRAIN, 25000},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+struct fan_step {
+	int on;
+	int off;
+	int rpm;
+};
+
+/* Note: Do not make the fan on/off point equal to 0 or 100 */
+static const struct fan_step fan_table0[] = {
+	{.on =  0, .off =  5, .rpm = 0},
+	{.on = 30, .off =  5, .rpm = 2180},
+	{.on = 49, .off = 46, .rpm = 2680},
+	{.on = 53, .off = 50, .rpm = 3300},
+	{.on = 58, .off = 54, .rpm = 3760},
+	{.on = 63, .off = 59, .rpm = 4220},
+	{.on = 68, .off = 64, .rpm = 4660},
+	{.on = 75, .off = 70, .rpm = 4900},
+};
+/* All fan tables must have the same number of levels */
+#define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0)
+
+static const struct fan_step *fan_table = fan_table0;
+
+
+static void cbi_init(void)
+{
+	uint32_t val;
+	if (cbi_get_board_version(&val) == EC_SUCCESS && val <= UINT8_MAX)
+		board_version = val;
+	CPRINTS("Board Version: 0x%02x", board_version);
+
+	if (cbi_get_oem_id(&val) == EC_SUCCESS && val < OEM_COUNT)
+		oem = val;
+	CPRINTS("OEM: %d", oem);
+
+	if (cbi_get_sku_id(&val) == EC_SUCCESS)
+		sku = val;
+	CPRINTS("SKU: 0x%08x", sku);
+}
+DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
+
+static void setup_bj(void)
+{
+	enum bj_adapter bj = (BJ_ADAPTER_135W_MASK & (1 << sku)) ?
+			BJ_135W_19V : BJ_90W_19V;
+	gpio_set_level(GPIO_U22_90W, bj == BJ_90W_19V);
+}
+
+static void board_init(void)
+{
+	setup_bj();
+
+	board_extpower();
+
+	gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+int fan_percent_to_rpm(int fan, int pct)
+{
+	static int current_level;
+	static int previous_pct;
+	int i;
+
+	/*
+	 * Compare the pct and previous pct, we have the three paths :
+	 *  1. decreasing path. (check the off point)
+	 *  2. increasing path. (check the on point)
+	 *  3. invariant path. (return the current RPM)
+	 */
+	if (pct < previous_pct) {
+		for (i = current_level; i >= 0; i--) {
+			if (pct <= fan_table[i].off)
+				current_level = i - 1;
+			else
+				break;
+		}
+	} else if (pct > previous_pct) {
+		for (i = current_level + 1; i < NUM_FAN_LEVELS; i++) {
+			if (pct >= fan_table[i].on)
+				current_level = i;
+			else
+				break;
+		}
+	}
+
+	if (current_level < 0)
+		current_level = 0;
+
+	previous_pct = pct;
+
+	if (fan_table[current_level].rpm !=
+		fan_get_rpm_target(FAN_CH(fan)))
+		cprints(CC_THERMAL, "Setting fan RPM to %d",
+			fan_table[current_level].rpm);
+
+	return fan_table[current_level].rpm;
+}
+
+__override void oz554_board_init(void)
+{
+	int pin_status = 0;
+
+	pin_status |= gpio_get_level(GPIO_PANEL_ID_0) << 0;
+	pin_status |= gpio_get_level(GPIO_PANEL_ID_1) << 1;
+	pin_status |= gpio_get_level(GPIO_PANEL_ID_2) << 2;
+
+	switch (pin_status) {
+	case 0x04:
+		CPRINTS("PANEL_LM_SSE2");
+		break;
+	case 0x05:
+		CPRINTS("PANEL_LM_SSK1");
+		/* Reigster 0x02: Setting LED current: 55(mA) */
+		if (oz554_set_config(2, 0x55))
+			CPRINTS("oz554 config failed");
+		break;
+	default:
+		CPRINTS("PANEL_UNKNOWN");
+		break;
+	}
+}
diff --git a/board/endeavour/board.h b/board/endeavour/board.h
new file mode 100644
index 0000000000..c9c54d3838
--- /dev/null
+++ b/board/endeavour/board.h
@@ -0,0 +1,234 @@
+/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Endeavour board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/*
+ * Allow dangerous commands.
+ * TODO: Remove this config before production.
+ */
+#undef  CONFIG_SYSTEM_UNLOCKED
+#define CONFIG_USB_PD_COMM_LOCKED
+
+/* EC */
+#define CONFIG_ADC
+#define CONFIG_BOARD_VERSION_CBI
+#define CONFIG_BOARD_HAS_RTC_RESET
+#define CONFIG_CRC8
+#define CONFIG_CEC
+#define CONFIG_CROS_BOARD_INFO
+#define CONFIG_DEDICATED_RECOVERY_BUTTON
+#define CONFIG_EMULATED_SYSRQ
+#define CONFIG_LED_COMMON
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP
+#define CONFIG_MKBP_USE_HOST_EVENT
+#define CONFIG_DPTF
+#define CONFIG_FLASH_SIZE 0x80000
+#define CONFIG_FPU
+#define CONFIG_I2C
+#define CONFIG_I2C_MASTER
+#undef  CONFIG_LID_SWITCH
+#define CONFIG_POWER_BUTTON_IGNORE_LID
+#define CONFIG_PWM
+#define CONFIG_LTO
+#define CONFIG_CHIP_PANIC_BACKUP
+#define CONFIG_SPI_FLASH_REGS
+#define CONFIG_SPI_FLASH_W25X40
+#define CONFIG_WATCHDOG_HELP
+#define CONFIG_WIRELESS
+#define CONFIG_WIRELESS_SUSPEND \
+	(EC_WIRELESS_SWITCH_WLAN | EC_WIRELESS_SWITCH_WLAN_POWER)
+#define WIRELESS_GPIO_WLAN GPIO_WLAN_OFF_L
+#define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_DX_WLAN
+#define WIRELESS_GPIO_WWAN GPIO_PP3300_DX_LTE
+#define CEC_GPIO_OUT GPIO_CEC_OUT
+#define CEC_GPIO_IN  GPIO_CEC_IN
+#define CEC_GPIO_PULL_UP GPIO_CEC_PULL_UP
+#define CONFIG_FANS 1
+#define CONFIG_FAN_RPM_CUSTOM
+#define CONFIG_THROTTLE_AP
+#define CONFIG_CHIPSET_CAN_THROTTLE
+#define CONFIG_PWM
+#define CONFIG_SUPPRESSED_HOST_COMMANDS \
+	EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_PD_GET_LOG_ENTRY
+
+/* EC console commands */
+#define CONFIG_CMD_BUTTON
+
+/* SOC */
+#define CONFIG_CHIPSET_SKYLAKE
+#define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
+#define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
+#define CONFIG_CHIPSET_RESET_HOOK
+#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+
+#define CONFIG_CMD_PD_CONTROL
+#define CONFIG_EXTPOWER_GPIO
+#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
+#define CONFIG_POWER_BUTTON
+#define CONFIG_POWER_BUTTON_X86
+#define CONFIG_POWER_BUTTON_INIT_IDLE
+#define CONFIG_POWER_COMMON
+#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
+#define CONFIG_DELAY_DSW_PWROK_TO_PWRBTN
+
+/* Sensor */
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_TMP432
+
+/* USB */
+#define CONFIG_USB_PD_ALT_MODE
+#define CONFIG_USB_PD_ALT_MODE_DFP
+#define CONFIG_USB_PD_DISCHARGE_TCPC
+#define CONFIG_USB_PD_LOGGING
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
+#define CONFIG_USB_PD_VBUS_DETECT_GPIO
+#define CONFIG_USB_PD_TCPM_MUX
+#define CONFIG_USB_PD_TCPM_TCPCI
+#define CONFIG_USB_PD_TCPM_PS8751
+#define CONFIG_USB_POWER_DELIVERY
+#define CONFIG_USBC_SS_MUX
+#define CONFIG_USBC_SS_MUX_DFP_ONLY
+#define CONFIG_USBC_VCONN
+
+/* USB-A config */
+#define CONFIG_USB_PORT_POWER_DUMB
+#define USB_PORT_COUNT 4
+
+/* Optional feature to configure npcx chip */
+#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
+#define NPCX_TACH_SEL2		1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
+
+/* I2C ports */
+#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
+#define I2C_PORT_EEPROM		NPCX_I2C_PORT0_1
+#define I2C_PORT_BACKLIGHT	NPCX_I2C_PORT1
+#define I2C_PORT_PMIC		NPCX_I2C_PORT2
+#define I2C_PORT_THERMAL	NPCX_I2C_PORT3
+
+/* I2C addresses */
+#define I2C_ADDR_TCPC0_FLAGS	0x0b
+#define I2C_ADDR_EEPROM_FLAGS	0x50
+
+/* Verify and jump to RW image on boot */
+#define CONFIG_VBOOT_EFS
+#define CONFIG_VBOOT_HASH
+#define CONFIG_VSTORE
+#define CONFIG_VSTORE_SLOT_COUNT 1
+
+/*
+ * LED backlight controller
+ */
+#define CONFIG_LED_DRIVER_OZ554
+
+/*
+ * Flash layout. Since config_flash_layout.h is included before board.h,
+ * we can only overwrite (=undef/define) these parameters here.
+ *
+ * Flash stores 3 images: RO, RW_A, RW_B. We divide the flash by 4.
+ * A public key is stored at the end of RO. Signatures are stored at the
+ * end of RW_A and RW_B, respectively.
+ */
+#define CONFIG_RW_B
+#define CONFIG_RW_B_MEM_OFF		CONFIG_RO_MEM_OFF
+#undef  CONFIG_RO_SIZE
+#define CONFIG_RO_SIZE			(CONFIG_FLASH_SIZE / 4)
+#undef  CONFIG_RW_SIZE
+#define CONFIG_RW_SIZE			CONFIG_RO_SIZE
+#define CONFIG_RW_A_STORAGE_OFF		CONFIG_RW_STORAGE_OFF
+#define CONFIG_RW_B_STORAGE_OFF		(CONFIG_RW_A_STORAGE_OFF + \
+					 CONFIG_RW_SIZE)
+#define CONFIG_RW_A_SIGN_STORAGE_OFF	(CONFIG_RW_A_STORAGE_OFF + \
+					 CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
+#define CONFIG_RW_B_SIGN_STORAGE_OFF	(CONFIG_RW_B_STORAGE_OFF + \
+					 CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
+
+#define CONFIG_RWSIG
+#define CONFIG_RWSIG_TYPE_RWSIG
+#define CONFIG_RSA
+#ifdef SECTION_IS_RO
+#define CONFIG_RSA_OPTIMIZED
+#endif
+#define CONFIG_SHA256
+#ifdef SECTION_IS_RO
+#define CONFIG_SHA256_UNROLLED
+#endif
+#define CONFIG_RSA_KEY_SIZE 3072
+#define CONFIG_RSA_EXPONENT_3
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum charge_port {
+	CHARGE_PORT_TYPEC0,
+	CHARGE_PORT_BARRELJACK,
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
+	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
+	TEMP_SENSOR_COUNT
+};
+
+enum adc_channel {
+	ADC_VBUS,
+	ADC_CH_COUNT
+};
+
+enum pwm_channel {
+	PWM_CH_LED_RED,
+	PWM_CH_LED_BLUE,
+	PWM_CH_FAN,
+	/* Number of PWM channels */
+	PWM_CH_COUNT
+};
+
+enum fan_channel {
+	FAN_CH_0,
+	/* Number of FAN channels */
+	FAN_CH_COUNT
+};
+
+enum mft_channel {
+	MFT_CH_0,
+	/* Number of MFT channels */
+	MFT_CH_COUNT
+};
+
+enum OEM_ID {
+	OEM_KARMA = 7,
+	/* Number of OEM IDs */
+	OEM_COUNT
+};
+
+/* TODO(crosbug.com/p/61098): Verify the numbers below. */
+/*
+ * delay to turn on the power supply max is ~16ms.
+ * delay to turn off the power supply max is about ~180ms.
+ */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
+
+/* delay to turn on/off vconn */
+#define PD_VCONN_SWAP_DELAY		5000   /* us */
+
+/* Board specific handlers */
+void board_reset_pd_mcu(void);
+void board_set_tcpc_power_mode(int port, int mode);
+void led_alert(int enable);
+void led_critical(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/endeavour/build.mk b/board/endeavour/build.mk
new file mode 100644
index 0000000000..69256da8a0
--- /dev/null
+++ b/board/endeavour/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_VARIANT:=npcx5m6g
+
+board-y=board.o
+board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
+board-y+=led.o
diff --git a/board/endeavour/dev_key.pem b/board/endeavour/dev_key.pem
new file mode 100644
index 0000000000..b72c787613
--- /dev/null
+++ b/board/endeavour/dev_key.pem
@@ -0,0 +1,39 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIG4gIBAAKCAYEAseZZZlXXDP+KrjqV+XhP0ZgPlU5mX4GCm27yzTqcKiFWLlHZ
+3f8seGG0lKNiL7WvHim8uSEDaPbp2us4uaJ6nTHEpbSGi2QVp90tE3aJG34HyKlg
+jcaE1r/0n6ynG/bf0Xx4O63Plp3Czi3TBYW49vT6+T/Jyfl2JpGQ9KNcD0umafsv
+uaEmdrLGrzjN8w1mFZfwscFkfVDh0cdiFNJ+UkTSpO9/yPapXbo4/lOMwdO9xILF
+cEZV9I7K7lBSvQ5Uep+w0SqNPTh2cGhoeEeDyH+Ce0LA8H7ZwbVnwLe1RswF9Wek
+uzqp9lMSNkkwMtTkumTuJLLGJX9rc0MVQTKgNV8wIzizf5lkCCBCJLf7aRBaeWCJ
+cXjKiavSPOZXDcnqCWqRJT3jN4ibAsU1GQtqLa8pTAi2wkE0fjuvAWK3NYuvpukg
+qNq2LI+BJkF4+dCZoeB1PDNyFNzdOFvkxj2+ImS3DLlPYVng4vHsTK1HRUUpL5Ag
+jjfMhMs4NC7HMOCTAgEDAoIBgHaZkO7j5LNVBx7RuVD63+EQCmOJmZUBAbz0od4n
+EsbA5B7hO+lUyFBBIw3CQXUjyhQb0yYWAkX58Tyc0HvBpxN2gxkjBFztY8U+Hgz5
+sLz+r9sblbPZreR/+GpzGhKklTZS+tJz37m+gd7JN1kD0KSjUft/29v7pBm2YKMX
+krTdGZv8ynvAxE8h2col3qII7rkP9cvWQv416+EvlriMVDbYjG30/9tPG5PRe1Q3
+syvifoMB2PWEOU20h0mK4dNe4d7E96s1Q+RTmTUtyipxUp6d4PIufAjMtM8yfkb0
+/0z81IsWQ0NOhefrMAi8TEcDkbyNSBPqHqbqH2FosFWo2cU3r6TXv2LdvFzc5BA+
+U6c+fXz7BDjv+NT3Bh98whKvTdJYcIgSg6vqzW7ZWJWWllZQtpJnQccIq4sPaL4S
+osFg8jd1kcbjVakCN0wYtfvMa/+WBZNNsZLUHoeIJvO7qnT7VKzhceoKHCJCMxNR
+Ypu5eELxCwebTXiImDqmFsKIawKBwQDpDjff6eatHbjmGV1elTyV5MLi95Tc0T7P
+FZHC1KLXkA/mEuXjAGfoZuLB5a3WmrA8r8fWNZoKV+0RBKIs3at1JFxZn9YiA0Hy
+5qmnYkXjMaY4p5AyO3eJsc2kbsh9r0cy2cb5GdwFDApeoVICoQh+dW9FpvIS+9AF
+0DVc2/Rg//cuXLlCMonF+PZVmDxRNhjBvwvRjxeowiu2ntI4sa83nHMhXI/RfvV4
+xcSng8gSIvabUmunDcPKvqO3rnpHzVECgcEAw2oFcHDAuZ1Xuopb2ghLRK3uLQVy
+BnqLu9QYk3OTe8C3PrNZ80R5MgtnZ0kP8bTZ4uE6MJ3+IMhPUCFqk9euGGdMUlU+
+SUmHie5CZPg4CwD4BUBy6dVdwId7aTxrdBOuGwwhYAhBsJxcfd3eNgiALcCoKsbi
+BLhjJ9Rch2rOsnpNJVwMvFMr6RM33oQrrufe4MBhDa/QD9yDtnDYH/KPO09E6AqU
+sMvBNsjbCC9rSYv+L9QkW8EUhT+wJIcqxUajAoHBAJtez+qb7x4T0JlmPj8OKGPt
+10H6Yz3g1IoOYSyNweUKtUQMmUIARUWZ7IFDyTm8dX3KhTl5EVw6ngtYbB3pHPjC
+6Du/5Bas1qHvG8TsLpd2btBvtXbST7EhM8L0hakfhMyRL1C76ANdXD8WNqxrWv74
+9NkZ9rdSiq6Kzj3n+ECqpMmTJiwhsS6l+Y5lfYt5ZdZ/XTZfZRssHSRp4XshH3po
+TMDoX+D/TlCD2G+tMAwXTxI28m9egocpwnp0UYUziwKBwQCCRq5K9dXRE4/RsZKR
+WtzYc/QeA6FZpwfSjWW3omJSgHopzOaiLaYhXO+aMLVLzeaXQNF1vqlrMDTgFkcN
+OnQQRN2MONQw26+xSYGYpXqyAKVY1aHxOOkrBPzw0vJNYnQSCBZABYEgaD2pPpQk
+BarJKxrHL0FYeuzFOD2vnInMUYjDkrMoN3KbYiU/AsfJ7+nrKutedTVf6FfO9eVq
+obTSNNiasbh13St52zywH5zbsql1OBg9K2MDf8rDBMcuLxcCgcBfM9FWZivdG2tJ
+5REvL0vPAQfcjVi4HUHvnaCuwMYEuF5T2Xf9P8d8ZflfWHaGlkl/qPvE897fns2l
+PZvvhRnr9GlHKt940ZOTI2v+hjlwcHGAAQc+p7BcKeUYLChwhVK/cZ9f6ZCotZNh
+543ecG4KZiJaqBZ/mDRaW7Py0w6lbOAzprrHF3ChvQ6VAllajoWx4CeINRcxX2vP
+bAPZxvt0gwpoHtUAsZo/bKEF0sM5qM/fK43gH5KhJeunq/xHO7E=
+-----END RSA PRIVATE KEY-----
diff --git a/board/endeavour/ec.tasklist b/board/endeavour/ec.tasklist
new file mode 100644
index 0000000000..6a1fae952c
--- /dev/null
+++ b/board/endeavour/ec.tasklist
@@ -0,0 +1,20 @@
+/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, 2048) \
+	/* Larger stack for RW verification (i.e. sha256, rsa) */ \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(PDCMD, pd_command_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 2048) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CEC, cec_task, NULL, TASK_STACK_SIZE)
diff --git a/board/endeavour/gpio.inc b/board/endeavour/gpio.inc
new file mode 100644
index 0000000000..6d959705b1
--- /dev/null
+++ b/board/endeavour/gpio.inc
@@ -0,0 +1,108 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+GPIO_INT(USB_C0_PD_INT_ODL,	PIN(3, 7), GPIO_INT_FALLING | GPIO_PULL_UP,	tcpc_alert_event)
+GPIO_INT(AC_PRESENT,		PIN(C, 1), GPIO_INT_BOTH,			extpower_interrupt)
+GPIO_INT(POWER_BUTTON_L,	PIN(0, 4), GPIO_INT_BOTH | GPIO_PULL_UP,	power_button_interrupt)	/* MECH_PWR_BTN_ODL */
+GPIO_INT(PANEL_BACKLIGHT_EN,	PIN(4, 4), GPIO_INT_RISING, backlight_enable_interrupt)
+
+GPIO_INT(PCH_SLP_S0_L,		PIN(7, 5), GPIO_INT_BOTH,			power_signal_interrupt)
+GPIO_INT(PCH_SLP_SUS_L,		PIN(6, 2), GPIO_INT_BOTH,			power_signal_interrupt)
+GPIO_INT(RSMRST_L_PGOOD,	PIN(B, 0), GPIO_INT_BOTH,			power_signal_interrupt)
+GPIO_INT(PMIC_DPWROK,		PIN(C, 7), GPIO_INT_BOTH,			power_signal_interrupt)
+GPIO_INT(WP_L,			PIN(9, 3), GPIO_INT_BOTH,			switch_interrupt)
+GPIO_INT(USB_C0_VBUS_WAKE_L,	PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP,	vbus0_evt)
+GPIO_INT(RECOVERY_L,		PIN(8, 2), GPIO_INT_BOTH, button_interrupt)	/* Recovery button */
+GPIO(PCH_RTCRST,		PIN(E, 7), GPIO_OUT_LOW)			/* RTCRST# to SOC */
+GPIO(WLAN_OFF_L,		PIN(7, 2), GPIO_OUT_LOW)			/* Disable WLAN */
+GPIO(PP3300_DX_WLAN,		PIN(A, 7), GPIO_OUT_LOW)			/* Enable WLAN 3.3V Power */
+GPIO(CPU_PROCHOT,		PIN(8, 1), GPIO_OUT_HIGH)			/* PROCHOT# to SOC */
+GPIO(PCH_ACPRESENT,		PIN(5, 0), GPIO_ODR_LOW)			/* ACOK to SOC */
+GPIO(PCH_WAKE_L,		PIN(A, 3), GPIO_ODR_HIGH)			/* Wake SOC */
+GPIO(PCH_RSMRST_L,		PIN(7, 0), GPIO_OUT_LOW)			/* RSMRST# to SOC */
+GPIO(PCH_PWRBTN_L,		PIN(7, 4), GPIO_ODR_HIGH)			/* Power Button to SOC */
+GPIO(EC_PLATFORM_RST,		PIN(4, 5), GPIO_OUT_LOW)			/* EC Reset to LDO_EN */
+GPIO(SYS_RESET_L,		PIN(6, 1), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
+GPIO(PMIC_SLP_SUS_L,		PIN(8, 5), GPIO_OUT_LOW)			/* SLP_SUS# to PMIC */
+GPIO(CCD_MODE_ODL,		PIN(6, 3), GPIO_INPUT)				/* Case Closed Debug Mode */
+GPIO(EC_HAVEN_RESET_ODL,	PIN(0, 2), GPIO_ODR_HIGH)			/* H1 Reset */
+GPIO(ENTERING_RW,		PIN(7, 6), GPIO_OUTPUT)				/* EC Entering RW */
+GPIO(PMIC_INT_L,		PIN(6, 0), GPIO_INPUT)				/* PMIC interrupt */
+GPIO(U22_90W,			PIN(3, 4), GPIO_OUTPUT | GPIO_PULL_DOWN)
+GPIO(POWER_RATE,		PIN(7, 1), GPIO_INPUT)				/* High: i3/5/7. Low: Celeron */
+GPIO(PP3300_USB_PD_EN,		PIN(6, 7), GPIO_OUT_HIGH)                       /* Initialize PP3300_USB_PD_EN as output high */
+
+GPIO(LAN_PWR_EN,		PIN(8, 3), GPIO_OUT_HIGH)			/* Ethernet power enabled */
+
+GPIO(PP5000_DX_NFC,		PIN(1, 5), GPIO_OUTPUT)
+
+GPIO(PP3300_DX_CAM,		PIN(1, 0), GPIO_OUT_HIGH)
+GPIO(CAM_PMIC_RST_L,		PIN(0, 7), GPIO_INPUT)
+
+GPIO(WLAN_PE_RST,		PIN(1, 2), GPIO_OUTPUT)
+GPIO(PP3300_DX_LTE,		PIN(0, 5), GPIO_OUT_LOW)
+GPIO(PP3300_DX_BASE,		PIN(1, 1), GPIO_OUT_LOW)
+
+/* I2C pins - these will be reconfigured for alternate function below */
+GPIO(I2C0_0_SCL,		PIN(B, 5), GPIO_INPUT)				/* EC_I2C_USB_C0_PD_SCL */
+GPIO(I2C0_0_SDA,		PIN(B, 4), GPIO_INPUT)				/* EC_I2C_USB_C0_PD_SDA */
+GPIO(I2C0_1_SCL,		PIN(B, 3), GPIO_INPUT)				/* EC_I2C_EEPROM_SCL */
+GPIO(I2C0_1_SDA,		PIN(B, 2), GPIO_INPUT)				/* EC_I2C_EEPROM_SDA */
+GPIO(I2C1_SCL,			PIN(9, 0), GPIO_INPUT)				/* EC_I2C_BAT_SCL */
+GPIO(I2C1_SDA,			PIN(8, 7), GPIO_INPUT)				/* EC_I2C_BAT_SDA */
+GPIO(I2C2_SCL,			PIN(9, 2), GPIO_INPUT)				/* EC_ROP_I2C_CLK */
+GPIO(I2C2_SDA,			PIN(9, 1), GPIO_INPUT)				/* EC_ROP_I2C_SDA */
+GPIO(I2C3_SCL,			PIN(D, 1), GPIO_INPUT)				/* EC_THEM_CLK */
+GPIO(I2C3_SDA,			PIN(D, 0), GPIO_INPUT)				/* EC_THEM_SDA */
+
+/* 5V enables: INPUT=1.5A, OUT_LOW=OFF, OUT_HIGH=3A */
+GPIO(USB_C0_5V_EN,		PIN(4, 2), GPIO_OUT_LOW | GPIO_PULL_UP)		/* C0 5V Enable */
+GPIO(USB_C0_VBUS_ILIM,		PIN(3, 5), GPIO_OUT_HIGH)
+GPIO(USB_C0_PD_RST_ODL,		PIN(0, 3), GPIO_OUT_LOW)			/* C0 PD Reset */
+GPIO(USB_C0_DP_HPD,		PIN(9, 4), GPIO_INPUT)				/* C0 DP Hotplug Detect */
+GPIO(USB_C0_TCPC_PWR,		PIN(8, 4), GPIO_OUT_LOW)			/* Enable C0 TCPC Power */
+GPIO(FAN_PWR_EN,		PIN(9, 5), GPIO_OUT_HIGH)			/* Fan power */
+GPIO(USB1_ENABLE,		PIN(3, 2), GPIO_OUT_LOW)			/* Rear port, bottom */
+GPIO(USB2_ENABLE,		PIN(C, 6), GPIO_OUT_LOW)			/* Rear port, top */
+GPIO(USB3_ENABLE,		PIN(A, 1), GPIO_OUT_LOW)			/* Rear port, single */
+GPIO(USB4_ENABLE,		PIN(0, 0), GPIO_OUT_LOW)			/* Front port 1 */
+GPIO(USB_A_CHARGE_EN_L,		PIN(A, 5), GPIO_OUT_LOW)
+
+GPIO(CEC_OUT,			PIN(3, 6), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
+GPIO(CEC_IN,			PIN(4, 0), GPIO_INPUT)
+GPIO(CEC_PULL_UP,		PIN(D, 3), GPIO_OUT_HIGH)
+GPIO(EC_EDID_WRITE_EN_L,	PIN(C, 3), GPIO_OUT_HIGH)			/* LOW to write EDID */
+
+/* Speaker */
+GPIO(SPKR5,			PIN(C, 2), GPIO_INPUT)				/* No function */
+
+GPIO(PANEL_ID_0,		PIN(C, 5), GPIO_INPUT)
+GPIO(PANEL_ID_1,		PIN(0, 1), GPIO_INPUT)
+GPIO(PANEL_ID_2,		PIN(B, 1), GPIO_INPUT)
+
+/* Test points */
+GPIO(TP121,			PIN(3, 3), GPIO_INPUT)
+GPIO(TP127,			PIN(6, 6), GPIO_INPUT)
+GPIO(TP128,			PIN(C, 4), GPIO_INPUT)
+GPIO(TP248,			PIN(5, 7), GPIO_INPUT)
+
+/* Alternate functions GPIO definitions */
+ALTERNATE(PIN_MASK(6, 0x30), 1, MODULE_UART, 0)		/* GPIO64-65 */		/* UART from EC to Servo */
+ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)		/* GPIO87 */		/* EC_I2C1_3V3_SDA */
+ALTERNATE(PIN_MASK(9, 0x01), 1, MODULE_I2C, 0)		/* GPIO90 */		/* EC_I2C1_3V3_SCL */
+ALTERNATE(PIN_MASK(9, 0x06), 1, MODULE_I2C, 0)		/* GPIO91-92 */		/* EC_I2C2_PMIC_3V3_SDA/SCL */
+ALTERNATE(PIN_MASK(A, 0x40), 1, MODULE_PWM, 0)		/* GPIOA6 */		/* TACH2 */
+ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)		/* GPIOB4-B5 */		/* EC_I2C0_0_USBC_3V3_SDA/SCL */
+ALTERNATE(PIN_MASK(B, 0x40), 1, MODULE_PWM, 0)		/* GPIOB6 */		/* EC_FAN_PWM */
+ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, 0)		/* GPOPB2-B3 */		/* EC_I2C0_1_3V3_SDA/SCL */
+ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0)		/* GPIOD0-D1 */		/* EC_I2C3_SENSOR_1V8_SDA/SCL */
+/* Alternate functions for LED PWM */
+ALTERNATE(PIN_MASK(8, 0x01), 1, MODULE_PWM, 0)		/* GPIO80 PWM3 Red*/
+ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)		/* GPOB7 PWM5 Green*/
diff --git a/board/endeavour/led.c b/board/endeavour/led.c
new file mode 100644
index 0000000000..f6d270c25b
--- /dev/null
+++ b/board/endeavour/led.c
@@ -0,0 +1,232 @@
+/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control for Endeavour
+ */
+
+#include "chipset.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "pwm.h"
+#include "timer.h"
+#include "util.h"
+
+const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_RED,
+	LED_BLUE,
+	LED_AMBER,
+
+	/* Number of colors, not a color itself */
+	LED_COLOR_COUNT
+};
+
+static int set_color_power(enum led_color color, int duty)
+{
+	int blue = 0;
+	int red = 0;
+
+	if (duty < 0 || 100 < duty)
+		return EC_ERROR_UNKNOWN;
+
+	switch (color) {
+	case LED_OFF:
+		break;
+	case LED_BLUE:
+		blue = 1;
+		break;
+	case LED_RED:
+		red = 1;
+		break;
+	case LED_AMBER:
+		blue = 1;
+		red = 1;
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+
+	if (red)
+		pwm_set_duty(PWM_CH_LED_RED, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_RED, 0);
+
+	if (blue)
+		pwm_set_duty(PWM_CH_LED_BLUE, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_BLUE, 0);
+
+	return EC_SUCCESS;
+}
+
+static int set_color(enum ec_led_id id, enum led_color color, int duty)
+{
+	switch (id) {
+	case EC_LED_ID_POWER_LED:
+		return set_color_power(color, duty);
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+}
+
+#define LED_PULSE_US		(2 * SECOND)
+/* 40 msec for nice and smooth transition. */
+#define LED_PULSE_TICK_US	(40 * MSEC)
+
+/* When pulsing is enabled, brightness is incremented by <duty_inc> every
+ * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
+ * likewise in LED_PULSE_US usec. */
+static struct {
+	uint32_t interval;
+	int duty_inc;
+	enum led_color color;
+	int duty;
+} led_pulse;
+
+#define LED_PULSE_TICK(interval, color) \
+	config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color))
+
+static void config_tick(uint32_t interval, int duty_inc, enum led_color color)
+{
+	led_pulse.interval = interval;
+	led_pulse.duty_inc = duty_inc;
+	led_pulse.color = color;
+	led_pulse.duty = 0;
+}
+
+static void pulse_power_led(enum led_color color)
+{
+	set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty);
+	if (led_pulse.duty + led_pulse.duty_inc > 100)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	else if (led_pulse.duty + led_pulse.duty_inc < 0)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	led_pulse.duty += led_pulse.duty_inc;
+}
+
+static void led_tick(void);
+DECLARE_DEFERRED(led_tick);
+static void led_tick(void)
+{
+	uint32_t elapsed;
+	uint32_t next = 0;
+	uint32_t start = get_time().le.lo;
+	static uint8_t pwm_enabled = 0;
+
+	if (!pwm_enabled) {
+		pwm_enable(PWM_CH_LED_RED, 1);
+		pwm_enable(PWM_CH_LED_BLUE, 1);
+		pwm_enabled = 1;
+	}
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		pulse_power_led(led_pulse.color);
+	elapsed = get_time().le.lo - start;
+	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
+	hook_call_deferred(&led_tick_data, next);
+}
+
+static void led_suspend(void)
+{
+	LED_PULSE_TICK(LED_PULSE_TICK_US, LED_BLUE);
+	led_tick();
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend, HOOK_PRIO_DEFAULT);
+
+static void led_shutdown(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown, HOOK_PRIO_DEFAULT);
+
+static void led_resume(void)
+{
+	/* Assume there is no race condition with led_tick, which also
+	 * runs in hook_task. */
+	hook_call_deferred(&led_tick_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_BLUE, 100);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
+
+void led_alert(int enable)
+{
+	if (enable) {
+		/* Overwrite the current signal */
+		config_tick(1 * SECOND, 100, LED_RED);
+		led_tick();
+	} else {
+		/* Restore the previous signal */
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			led_resume();
+		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
+			led_suspend();
+		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			led_shutdown();
+	}
+}
+
+void led_critical(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
+}
+
+static int command_led(int argc, char **argv)
+{
+	enum ec_led_id id = EC_LED_ID_POWER_LED;
+
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	if (!strcasecmp(argv[1], "debug")) {
+		led_auto_control(id, !led_auto_control_is_enabled(id));
+		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
+	} else if (!strcasecmp(argv[1], "off")) {
+		set_color(id, LED_OFF, 0);
+	} else if (!strcasecmp(argv[1], "red")) {
+		set_color(id, LED_RED, 100);
+	} else if (!strcasecmp(argv[1], "blue")) {
+		set_color(id, LED_BLUE, 100);
+	} else if (!strcasecmp(argv[1], "amber")) {
+		set_color(id, LED_AMBER, 100);
+	} else if (!strcasecmp(argv[1], "alert")) {
+		led_alert(1);
+	} else if (!strcasecmp(argv[1], "crit")) {
+		led_critical();
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(led, command_led,
+			"[debug|red|blue|amber|off|alert|crit]",
+			"Turn on/off LED.");
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_RED] = 100;
+	brightness_range[EC_LED_COLOR_BLUE] = 100;
+	brightness_range[EC_LED_COLOR_AMBER] = 100;
+}
+
+int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_RED])
+		return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]);
+	else if (brightness[EC_LED_COLOR_BLUE])
+		return set_color(id, LED_BLUE, brightness[EC_LED_COLOR_BLUE]);
+	else if (brightness[EC_LED_COLOR_AMBER])
+		return set_color(id, LED_AMBER, brightness[EC_LED_COLOR_AMBER]);
+	else
+		return set_color(id, LED_OFF, 0);
+}
diff --git a/board/endeavour/usb_pd_policy.c b/board/endeavour/usb_pd_policy.c
new file mode 100644
index 0000000000..2090184604
--- /dev/null
+++ b/board/endeavour/usb_pd_policy.c
@@ -0,0 +1,320 @@
+/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "atomic.h"
+#include "extpower.h"
+#include "charge_manager.h"
+#include "common.h"
+#include "console.h"
+#include "driver/tcpm/anx74xx.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "registers.h"
+#include "system.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+
+#define PDO_FIXED_FLAGS (PDO_FIXED_EXTERNAL | \
+			 PDO_FIXED_DATA_SWAP | \
+			 PDO_FIXED_COMM_CAP)
+
+const uint32_t pd_src_pdo[] = {
+	PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
+};
+const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
+
+void pd_transition_voltage(int idx)
+{
+	/* No-operation: we are always 5V */
+}
+
+int board_vbus_source_enabled(int port)
+{
+	if (port != 0)
+		return 0;
+	return gpio_get_level(GPIO_USB_C0_5V_EN);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	/* Enable VBUS source */
+	gpio_set_level(GPIO_USB_C0_5V_EN, 1);
+
+	/* notify host of power info change */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS; /* we are ready */
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS source */
+	gpio_set_level(GPIO_USB_C0_5V_EN, 0);
+
+	/* notify host of power info change */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return !gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L);
+}
+
+int pd_board_checks(void)
+{
+	return EC_SUCCESS;
+}
+
+int pd_check_data_swap(int port, int data_role)
+{
+	/* Allow data swap if we are a UFP, otherwise don't allow */
+	return (data_role == PD_ROLE_UFP) ? 1 : 0;
+}
+
+void pd_execute_data_swap(int port, int data_role)
+{
+}
+
+void pd_check_pr_role(int port, int pr_role, int flags)
+{
+}
+
+void pd_check_dr_role(int port, int dr_role, int flags)
+{
+	/* If UFP, try to switch to DFP */
+	if ((flags & PD_FLAGS_PARTNER_DR_DATA) && dr_role == PD_ROLE_UFP)
+		pd_request_data_swap(port);
+}
+
+/* ----------------- Vendor Defined Messages ------------------ */
+const struct svdm_response svdm_rsp = {
+	.identity = NULL,
+	.svids = NULL,
+	.modes = NULL,
+};
+
+int pd_custom_vdm(int port, int cnt, uint32_t *payload,
+		  uint32_t **rpayload)
+{
+	int cmd = PD_VDO_CMD(payload[0]);
+	uint16_t dev_id = 0;
+	int is_rw, is_latest;
+
+	/* make sure we have some payload */
+	if (cnt == 0)
+		return 0;
+
+	switch (cmd) {
+	case VDO_CMD_VERSION:
+		/* guarantee last byte of payload is null character */
+		*(payload + cnt - 1) = 0;
+		CPRINTF("version: %s\n", (char *)(payload+1));
+		break;
+	case VDO_CMD_READ_INFO:
+	case VDO_CMD_SEND_INFO:
+		/* copy hash */
+		if (cnt == 7) {
+			dev_id = VDO_INFO_HW_DEV_ID(payload[6]);
+			is_rw = VDO_INFO_IS_RW(payload[6]);
+
+			is_latest = pd_dev_store_rw_hash(port,
+							 dev_id,
+							 payload + 1,
+							  is_rw ?
+							 SYSTEM_IMAGE_RW :
+							 SYSTEM_IMAGE_RO);
+			/*
+			 * Send update host event unless our RW hash is
+			 * already known to be the latest update RW.
+			 */
+			if (!is_rw || !is_latest)
+				pd_send_host_event(PD_EVENT_UPDATE_DEVICE);
+
+			CPRINTF("DevId:%d.%d SW:%d RW:%d\n",
+				HW_DEV_ID_MAJ(dev_id),
+				HW_DEV_ID_MIN(dev_id),
+				VDO_INFO_SW_DBG_VER(payload[6]),
+				is_rw);
+		} else if (cnt == 6) {
+			/* really old devices don't have last byte */
+			pd_dev_store_rw_hash(port, dev_id, payload + 1,
+					     SYSTEM_IMAGE_UNKNOWN);
+		}
+		break;
+	case VDO_CMD_CURRENT:
+		CPRINTF("Current: %dmA\n", payload[1]);
+		break;
+	case VDO_CMD_FLIP:
+		usb_mux_flip(port);
+		break;
+#ifdef CONFIG_USB_PD_LOGGING
+	case VDO_CMD_GET_LOG:
+		pd_log_recv_vdm(port, cnt, payload);
+		break;
+#endif /* CONFIG_USB_PD_LOGGING */
+	}
+
+	return 0;
+}
+
+static int dp_flags[CONFIG_USB_PD_PORT_MAX_COUNT];
+static uint32_t dp_status[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+static void svdm_safe_dp_mode(int port)
+{
+	/* make DP interface safe until configure */
+	dp_flags[port] = 0;
+	dp_status[port] = 0;
+	usb_mux_set(port, TYPEC_MUX_NONE,
+		USB_SWITCH_CONNECT, pd_get_polarity(port));
+}
+
+static int svdm_enter_dp_mode(int port, uint32_t mode_caps)
+{
+	/* Only enter mode if device is DFP_D capable */
+	if (mode_caps & MODE_DP_SNK) {
+		pd_log_event(PD_EVENT_VIDEO_DP_MODE,
+			     PD_LOG_PORT_SIZE(port, 0), 1, NULL);
+		svdm_safe_dp_mode(port);
+		return 0;
+	}
+
+	return -1;
+}
+
+static int svdm_dp_status(int port, uint32_t *payload)
+{
+	int opos = pd_alt_mode(port, USB_SID_DISPLAYPORT);
+
+	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
+			 CMD_DP_STATUS | VDO_OPOS(opos));
+	payload[1] = VDO_DP_STATUS(0, /* HPD IRQ  ... not applicable */
+				   0, /* HPD level ... not applicable */
+				   0, /* exit DP? ... no */
+				   0, /* usb mode? ... no */
+				   0, /* multi-function ... no */
+				   (!!(dp_flags[port] & DP_FLAGS_DP_ON)),
+				   0, /* power low? ... no */
+				   (!!(dp_flags[port] & DP_FLAGS_DP_ON)));
+	return 2;
+};
+
+static int svdm_dp_config(int port, uint32_t *payload)
+{
+	int opos = pd_alt_mode(port, USB_SID_DISPLAYPORT);
+	int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
+	int pin_mode = pd_dfp_dp_get_pin_mode(port, dp_status[port]);
+
+	if (!pin_mode)
+		return 0;
+
+	usb_mux_set(port, mf_pref ? TYPEC_MUX_DOCK : TYPEC_MUX_DP,
+		    USB_SWITCH_CONNECT, pd_get_polarity(port));
+
+	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
+			 CMD_DP_CONFIG | VDO_OPOS(opos));
+	payload[1] = VDO_DP_CFG(pin_mode,      /* pin mode */
+				1,             /* DPv1.3 signaling */
+				2);            /* UFP connected */
+	return 2;
+};
+
+static void svdm_dp_post_config(int port)
+{
+	const struct usb_mux *mux = &usb_muxes[port];
+
+	dp_flags[port] |= DP_FLAGS_DP_ON;
+	if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING))
+		return;
+	mux->hpd_update(port, 1, 0);
+}
+
+static int svdm_dp_attention(int port, uint32_t *payload)
+{
+	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
+	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
+	const struct usb_mux *mux = &usb_muxes[port];
+
+	dp_status[port] = payload[1];
+	if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
+		if (lvl)
+			dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
+		return 1;
+	}
+	mux->hpd_update(port, lvl, irq);
+
+	/* ack */
+	return 1;
+}
+
+static void svdm_exit_dp_mode(int port)
+{
+	const struct usb_mux *mux = &usb_muxes[port];
+
+	pd_log_event(PD_EVENT_VIDEO_DP_MODE,
+		     PD_LOG_PORT_SIZE(port, 0), 0, NULL);
+	svdm_safe_dp_mode(port);
+	mux->hpd_update(port, 0, 0);
+}
+
+static int svdm_enter_gfu_mode(int port, uint32_t mode_caps)
+{
+	/* Always enter GFU mode */
+	return 0;
+}
+
+static void svdm_exit_gfu_mode(int port)
+{
+}
+
+static int svdm_gfu_status(int port, uint32_t *payload)
+{
+	/*
+	 * This is called after enter mode is successful, send unstructured
+	 * VDM to read info.
+	 */
+	pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_READ_INFO, NULL, 0);
+	return 0;
+}
+
+static int svdm_gfu_config(int port, uint32_t *payload)
+{
+	return 0;
+}
+
+static int svdm_gfu_attention(int port, uint32_t *payload)
+{
+	return 0;
+}
+
+const struct svdm_amode_fx supported_modes[] = {
+	{
+		.svid = USB_SID_DISPLAYPORT,
+		.enter = &svdm_enter_dp_mode,
+		.status = &svdm_dp_status,
+		.config = &svdm_dp_config,
+		.post_config = &svdm_dp_post_config,
+		.attention = &svdm_dp_attention,
+		.exit = &svdm_exit_dp_mode,
+	},
+	{
+		.svid = USB_VID_GOOGLE,
+		.enter = &svdm_enter_gfu_mode,
+		.status = &svdm_gfu_status,
+		.config = &svdm_gfu_config,
+		.attention = &svdm_gfu_attention,
+		.exit = &svdm_exit_gfu_mode,
+	}
+};
+const int supported_modes_cnt = ARRAY_SIZE(supported_modes);