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| author | Vijay Hiremath <vijay.p.hiremath@intel.com> | 2019-12-05 15:32:00 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-12-06 02:41:40 +0000 |
| commit | 93ff538d4c637860e19130c8d47f26081eb8a35c (patch) | |
| tree | ea7d4f42c7a466337c2fb86082f6d2d2f5f2d985 | |
| parent | 436ab9db9a0f999ac3452f8f26d4fb7ad4d4802c (diff) | |
| download | chrome-ec-93ff538d4c637860e19130c8d47f26081eb8a35c.tar.gz | |
volteer: Keep RSMRST# pin low at init
Keeping the RSMRST# pin is low at init based on the TGL
PDG power sequence Timing Diagram.
BUG=b:145767544
BRANCH=none
TEST=Verified on scope, RSMRST# pin is low at init
Change-Id: Ia5d5c76ce3f173d1c283da706dd1113ce1dad550
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954875
Reviewed-by: Keith Short <keithshort@chromium.org>
| -rw-r--r-- | board/volteer/gpio.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/volteer/gpio.inc b/board/volteer/gpio.inc index d18e272f12..5f6c213adf 100644 --- a/board/volteer/gpio.inc +++ b/board/volteer/gpio.inc @@ -75,7 +75,7 @@ GPIO(EC_RST_ODL, PIN(0, 2), GPIO_INT_BOTH | /* AP/PCH Signals */ GPIO(EC_PCH_SYS_PWROK, PIN(3, 7), GPIO_OUT_LOW) -GPIO(EC_PCH_RSMRST_ODL, PIN(A, 6), GPIO_ODR_HIGH) /* TODO - b/140950085 - implement TGL sequencing requirement */ +GPIO(EC_PCH_RSMRST_ODL, PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */ GPIO(EC_PCH_PWR_BTN_ODL, PIN(C, 1), GPIO_ODR_HIGH) GPIO(EC_PCH_RTCRST, PIN(7, 6), GPIO_OUT_LOW) GPIO(EC_PCH_WAKE_ODL, PIN(7, 4), GPIO_ODR_HIGH) |