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| author | Anton Staaf <robotboy@chromium.org> | 2015-08-10 14:49:34 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-08-11 19:52:40 +0000 |
| commit | fba4f335a9a78f4112980fcf1cc36d44cfda0406 (patch) | |
| tree | 390ce8ae7c5791ee787f347609efa2fbcf41f615 | |
| parent | 3cbc31aec352ab104dc8809d57cec13dfa27aa35 (diff) | |
| download | chrome-ec-fba4f335a9a78f4112980fcf1cc36d44cfda0406.tar.gz | |
cortex-m0: Constrain target register in atomic read
One more register constaint needed to be added to the cortex-m0 atomic
inline assembly. Vincent fixed all the others. The requirement for
ARMv6-m includes that the target load register be one of the low
registers as well.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: Ie44e824cafcc9b862ade664e3016cc34886cdf6e
Reviewed-on: https://chromium-review.googlesource.com/292435
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
| -rw-r--r-- | core/cortex-m0/atomic.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/core/cortex-m0/atomic.h b/core/cortex-m0/atomic.h index 32260ada07..e2df0f2a93 100644 --- a/core/cortex-m0/atomic.h +++ b/core/cortex-m0/atomic.h @@ -56,7 +56,7 @@ static inline uint32_t atomic_read_clear(uint32_t volatile *addr) " ldr %0, [%1]\n" " str %2, [%1]\n" " cpsie i\n" - : "=&r" (ret) + : "=&b" (ret) : "b" (addr), "r" (0) : "cc"); return ret; |