coil: cleanup commentsstabilize-rust-13720.B-cr50_stab

BUG=b:175244613
TEST=make buildall -j

Change-Id: Icbd143b072fdd5df3b67d7e5a09ee6c01a77f6b9
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2622889
Reviewed-by: Namyoon Woo <namyoon@chromium.org>

25 files changed, 129 insertions, 110 deletions

diff --git a/board/cr50/gpio.inc b/board/cr50/gpio.inc
index 887e2f4807..8fb67bd425 100644
--- a/board/cr50/gpio.inc
+++ b/board/cr50/gpio.inc
@@ -301,7 +301,7 @@ PINMUX(GPIO(DETECT_SERVO),      B5, DIO_INPUT)
 */
 
 /*
- * Both SPI master and slave buses are wired directly to specific pads
+ * Both SPI controller and peripheral buses are wired directly to specific pads
  *
  * If CONFIG_SPP is defined, these pads are used:
  *   DIOA2  = SPS_MOSI  (input)
diff --git a/board/cr50/usb_spi.c b/board/cr50/usb_spi.c
index a58e14789a..4ba11d6f30 100644
--- a/board/cr50/usb_spi.c
+++ b/board/cr50/usb_spi.c
@@ -208,7 +208,7 @@ static void enable_ap_spi(uint8_t custom_reset)
 }
 
 /**
- * Enable the pin mux to the SPI master port.
+ * Enable the pin mux to the SPI controller port.
  */
 static void enable_spi_pinmux(void)
 {
@@ -235,7 +235,7 @@ static void enable_spi_pinmux(void)
 }
 
 /**
- * Disable the pin mux to the SPI master port.
+ * Disable the pin mux to the SPI controller port.
  */
 static void disable_spi_pinmux(void)
 {
diff --git a/board/host/board.h b/board/host/board.h
index c42d0e0536..29623c0ca7 100644
--- a/board/host/board.h
+++ b/board/host/board.h
@@ -75,7 +75,7 @@ enum {
 
 /* Configuration for fake Fingerprint Sensor */
 #define CONFIG_SPI_CONTROLLER
-#define CONFIG_SPI_FP_PORT    1 /* SPI1: third master config */
+#define CONFIG_SPI_FP_PORT    1 /* SPI1: third controller config */
 
 /* UART indexes (use define rather than enum to expand them) */
 enum {
diff --git a/chip/g/gpio.c b/chip/g/gpio.c
index f55e0fad35..a113419874 100644
--- a/chip/g/gpio.c
+++ b/chip/g/gpio.c
@@ -306,15 +306,19 @@ static void connect_pinmux(struct pinmux const *p)
 	int is_input;
 
 	if (p->flags & DIO_ENABLE_DIRECT_INPUT) {
-		/* We don't have to setup any muxes for directly connected
+		/*
+		 * We don't have to setup any muxes for directly connected
 		 * pads. The only ones that we are likely to ever care about
-		 * are tied to the SPS and SPI peripherals, and they're all
-		 * inouts, so we can just enable the digital input for them
-		 * regardless. */
+		 * are tied to the SPP and SPI peripherals, and they're all
+		 * inputs, so we can just enable the digital input for them
+		 * regardless.
+		 */
 		is_input = 1;
 	} else {
-		/* Pads that must be muxed to specific GPIOs or peripherals may
-		 * or may not be inputs. We'll check those individually. */
+		/*
+		 * Pads that must be muxed to specific GPIOs or peripherals may
+		 * or may not be inputs. We'll check those individually.
+		 */
 		if (p->flags & DIO_TO_PERIPHERAL)
 			is_input = connect_dio_to_peripheral(p);
 		else
diff --git a/chip/g/i2cp.c b/chip/g/i2cp.c
index 09d7235be6..ce98140289 100644
--- a/chip/g/i2cp.c
+++ b/chip/g/i2cp.c
@@ -203,7 +203,7 @@ DECLARE_DEFERRED(poll_read_state);
  * happens to fail and stops clocking.
  *
  * For example when the i2cp driver is:
- * 1) Transmitting an ACK for the slave address byte.
+ * 1) Transmitting an ACK for the peripheral address byte.
  * 2) Transmitting an ACK for a write transaction.
  * 3) Transmitting byte data for a read transaction.
  *
@@ -216,8 +216,8 @@ DECLARE_DEFERRED(poll_read_state);
  * We don't have to deal with the scenario where the driver gets stuck
  * transmitting a 1 on SDA since the controller can recover the bus by issuing a
  * normal transaction. The controller will at minimum clock 9 times on any
- * transaction. This is enough for the slave to complete its current operation
- * and NACK.
+ * transaction. This is enough for the peripheral to complete its current
+ * operation and NACK.
  */
 static void poll_read_state(void)
 {
diff --git a/chip/g/spi_controller.c b/chip/g/spi_controller.c
index 90ad033e46..912520e52f 100644
--- a/chip/g/spi_controller.c
+++ b/chip/g/spi_controller.c
@@ -23,14 +23,16 @@
  * by using the largest uint8_t clock divider of 256 (~235kHz). */
 #define SPI_TRANSACTION_TIMEOUT_USEC (5 * MSEC)
 
-/* There are two SPI masters or ports on this chip. */
+/* There are two SPI controllers or ports on this chip. */
 #define SPI_NUM_PORTS 2
 
 static struct mutex spi_mutex[SPI_NUM_PORTS];
 static enum spi_clock_mode clock_mode[SPI_NUM_PORTS];
 
-/* The Cr50 SPI master is not DMA auto-fill/drain capable, so async and flush
- * are not defined on purpose. */
+/*
+ * The Cr50 SPI controller is not DMA auto-fill/drain capable, so async and
+ * flush are not defined on purpose.
+ */
 int spi_transaction(const struct spi_device_t *spi_device,
 		    const uint8_t *txdata, int txlen,
 		    uint8_t *rxdata, int rxlen)
@@ -41,8 +43,10 @@ int spi_transaction(const struct spi_device_t *spi_device,
 	int transaction_size = 0;
 	int rxoffset = 0;
 
-	/* If SPI0's passthrough is enabled, SPI0 is not available unless the
-	 * SPS's BUSY bit is set. */
+	/*
+	 * If SPI0's passthrough is enabled, SPI0 is not available unless the
+	 * SPP's BUSY bit is set.
+	 */
 	if (port == 0) {
 		if (GREAD_FIELD_I(SPI, port, CTRL, ENPASSTHRU) &&
 		    !GREAD(SPS, EEPROM_BUSY_STATUS))
@@ -94,7 +98,7 @@ int spi_transaction(const struct spi_device_t *spi_device,
 	GWRITE_FIELD_I(SPI, port, XACT, SIZE, transaction_size - 1);
 	GWRITE_FIELD_I(SPI, port, XACT, START, 1);
 
-	/* Wait for the SPI master to finish the transaction. */
+	/* Wait for the SPI controller to finish the transaction. */
 	timeout.val = get_time().val + SPI_TRANSACTION_TIMEOUT_USEC;
 	while (!GREAD_FIELD_I(SPI, port, ISTATE, TXDONE)) {
 		/* Give up if the deadline has been exceeded. */
@@ -136,10 +140,11 @@ void set_spi_clock_mode(int port, enum spi_clock_mode mode)
 }
 
 /*
- * Configure the SPI0 master's passthrough mode. Note:
+ * Configure the SPI0 controller's passthrough mode. Note:
  * 1) This must be called after the SPI port is enabled.
- * 2) Passthrough cannot be safely disabled while the SPI slave port is active
- *    and the SPI slave port's status register's BUSY bit is not set.
+ * 2) Passthrough cannot be safely disabled while the SPI peripheral port is
+ *    active and the SPI peripheral port's status register's BUSY bit is not
+ *    set.
  */
 void configure_spi0_passthrough(int enable)
 {
@@ -201,7 +206,7 @@ int spi_enable(int port, int enable)
 		/* Set the clock divider, where freq / (div + 1). */
 		GWRITE_FIELD_I(SPI, port, CTRL, IDIV, max_div);
 
-		/* Master's CS is active low. */
+		/* Controller's CS is active low. */
 		GWRITE_FIELD_I(SPI, port, CTRL, CSBPOL, 0);
 
 		/* Byte 0 bit 7 is first in each double word in the buffers. */
@@ -255,9 +260,11 @@ static void spi_init(void)
 		/* Configure the SPI ports to default to mode0. */
 		set_spi_clock_mode(i, SPI_CLOCK_MODE0);
 
-		/* Ensure the SPI ports are disabled to prevent us from
+		/*
+		 * Ensure the SPI ports are disabled to prevent us from
 		 * interfering with the main chipset when we're not explicitly
-		 * using the SPI bus. */
+		 * using the SPI bus.
+		 */
 		spi_enable(i, 0);
 	}
 }
diff --git a/chip/g/spp.c b/chip/g/spp.c
index 5162b5652c..a4b4eaedaa 100644
--- a/chip/g/spp.c
+++ b/chip/g/spp.c
@@ -15,7 +15,7 @@
 #include "watchdog.h"
 
 /*
- * This file is a driver for the CR50 SPS (SPI slave) controller. The
+ * This file is a driver for the CR50 SPP (SPI peripheral) controller. The
  * controller deploys a 2KB buffer split evenly between receive and transmit
  * directions.
  *
@@ -70,7 +70,7 @@ void spp_tx_status(uint8_t byte)
 }
 
 /*
- * Push data to the SPS TX FIFO
+ * Push data to the SPP TX FIFO
  * @param data Pointer to 8-bit data
  * @param data_size Number of bytes to transmit
  * @return : actual number of bytes placed into tx fifo
@@ -116,7 +116,7 @@ int spp_transmit(uint8_t *data, size_t data_size)
 			fifo_contents = *spp_tx_fifo;
 			do {
 				/*
-				 * CR50 SPS controller does not allow byte
+				 * CR50 SPP controller does not allow byte
 				 * accesses for writes into the FIFO, so read
 				 * modify/write is required. Tracked under
 				 * http://b/20894727
@@ -164,7 +164,7 @@ int spp_transmit(uint8_t *data, size_t data_size)
 static int spp_cs_asserted(void)
 {
 	/*
-	 * Read the current value on the SPS CS line and return the iversion
+	 * Read the current value on the SPP CS line and return the iversion
 	 * of it (CS is active low).
 	 */
 	return !GREAD_FIELD(SPS, VAL, CSB);
@@ -255,7 +255,7 @@ int spp_register_rx_handler(enum spp_mode mode, rx_handler_f rx_handler,
 	return 0;
 }
 
-/* Function that sets up for SPS to enable INT_AP_L extension. */
+/* Function that sets up for SPP to enable INT_AP_L extension. */
 static void spp_int_ap_extension_enable_(void)
 {
 	enable_cs_assert_irq_();
@@ -266,8 +266,8 @@ static void spp_int_ap_extension_enable_(void)
 static void spp_init(void)
 {
 	/*
-	 * Check to see if slave SPI interface is required by the board before
-	 * initializing it. If SPI option is not set, then just return.
+	 * Check to see if peripheral SPI interface is required by the board
+	 * before initializing it. If SPI option is not set, then just return.
 	 */
 	if (!board_tpm_uses_spi())
 		return;
@@ -459,7 +459,7 @@ DECLARE_IRQ(GC_IRQNUM_SPS0_CS_ASSERT_INTR, sps0_cs_assert_interrupt_, 1);
 
 #ifdef CONFIG_SPP_TEST
 
-/* Function to test SPS driver. It expects the host to send SPI frames of size
+/* Function to test SPP driver. It expects the host to send SPI frames of size
  * <size> (not exceeding 1100) of the following format:
  *
  * <size/256> <size%256> [<size> bytes of payload]
diff --git a/chip/g/spp_tpm.c b/chip/g/spp_tpm.c
index a2bb4be171..bdd58b7be3 100644
--- a/chip/g/spp_tpm.c
+++ b/chip/g/spp_tpm.c
@@ -21,30 +21,31 @@
  *
  * ANYWAY, The goal of the TPM protocol is to provide read and write access to
  * device registers over the SPI bus. It is defined as follows (note that the
- * master clocks the bus, but both master and slave transmit data
+ * controller clocks the bus, but both controller and peripheral transmit data
  * simultaneously).
  *
- * Each transaction starts with the master clocking the bus to transfer 4
+ * Each transaction starts with the controller clocking the bus to transfer 4
  * bytes:
  *
- * The master sends 4 bytes:       [R/W+size-1] [Addr] [Addr] [Addr]
- * The slave also sends 4 bytes:       [xx]      [xx]   [xx]   [x?]
+ * The controller sends 4 bytes:       [R/W+size-1] [Addr] [Addr] [Addr]
+ * The peripheral also sends 4 bytes:  [xx]      [xx]   [xx]   [x?]
  *
- * Bytes sent by the master define the direction and size (1-64 bytes) of the
- * data transfer, and the address of the register to access.
+ * Bytes sent by the controller define the direction and size (1-64 bytes) of
+ * the data transfer, and the address of the register to access.
  *
- * The final bit of the 4th slave response byte determines whether or not the
- * slave needs some extra time. If that bit is 1, the master can IMMEDIATELY
- * clock in (or out) the number of bytes it specified with the header byte 0.
+ * The final bit of the 4th peripheral response byte determines whether or not
+ * the peripheral needs some extra time. If that bit is 1, the controller can
+ * IMMEDIATELY clock in (or out) the number of bytes it specified with the
+ * header byte 0.
  *
- * If the final bit of the 4th response byte is 0, the master clocks eight more
- * bits and looks again at the new received byte. It repeats this process
+ * If the final bit of the 4th response byte is 0, the controller clocks eight
+ * more bits and looks again at the new received byte. It repeats this process
  * (clock 8 bits, look at last bit) as long as every eighth bit is 0.
  *
- * When the slave is ready to proceed with the data transfer, it returns a 1
- * for the final bit of the response byte, at which point the master has to
- * resume transferring valid data for write transactions or to start reading
- * bytes sent by the slave for read transactions.
+ * When the peripheral is ready to proceed with the data transfer, it returns a
+ * 1 for the final bit of the response byte, at which point the controller has
+ * to resume transferring valid data for write transactions or to start reading
+ * bytes sent by the peripheral for read transactions.
  *
  * So here's what a 4-byte write of value of 0x11223344 to register 0xAABBCC
  * might look like:
@@ -53,9 +54,10 @@
  *   MOSI: 03 aa bb cc xx xx xx 11 22 33 44
  *   MISO: xx xx xx x0 x0 x0 x1 xx xx xx xx
  *
- * Bit 0 of MISO xfer #4 is 0, indicating that the slave needs to stall. The
- * slave stalled for three bytes before it was ready to continue accepting the
- * input data from the master. The slave released the stall in xfer #7.
+ * Bit 0 of MISO xfer #4 is 0, indicating that the peripheral needs to stall.
+ * The peripheral stalled for three bytes before it was ready to continue
+ * accepting the input data from the controller. The peripheral released the
+ * stall in xfer #7.
  *
  * Here's a 4-byte read from register 0xAABBCC:
  *
@@ -63,8 +65,8 @@
  *   MOSI: 83 aa bb cc xx xx xx xx xx xx xx
  *   MISO: xx xx xx x0 x0 x0 x1 11 22 33 44
  *
- * As before, the slave stalled the read for three bytes and indicated it was
- * done stalling at xfer #7.
+ * As before, the peripheral stalled the read for three bytes and indicated it
+ * was done stalling at xfer #7.
  *
  * Note that the ONLY place where a stall can be initiated is the last bit of
  * the fourth MISO byte of the transaction. Once the stall is released,
@@ -85,7 +87,7 @@
 /*
  * Incoming messages are collected here until they're ready to process. The
  * buffer will start with a four-byte header, followed by whatever data
- * is sent by the master (none for a read, 1 to 64 bytes for a write).
+ * is sent by the controller (none for a read, 1 to 64 bytes for a write).
  */
 #define RXBUF_MAX 512			/* chosen arbitrarily */
 static uint8_t rxbuf[RXBUF_MAX];
@@ -176,7 +178,7 @@ static void process_rx_data(uint8_t *data, size_t data_size, int cs_deasserted)
 		}
 
 		/*
-		 * Write the new idle byte value, to signal the master to
+		 * Write the new idle byte value, to signal the controller to
 		 * proceed with data.
 		 */
 		spp_tx_status(TPM_STALL_DEASSERT);
diff --git a/chip/host/spi_controller.c b/chip/host/spi_controller.c
index 83bde96163..e7dfae481e 100644
--- a/chip/host/spi_controller.c
+++ b/chip/host/spi_controller.c
@@ -2,7 +2,7 @@
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
- * Dummy Master SPI driver for unit test.
+ * Dummy SPI Controller driver for unit test.
  */
 
 #include <stdint.h>
diff --git a/chip/lm4/gpio.c b/chip/lm4/gpio.c
index 65d6548f90..39baae3bf6 100644
--- a/chip/lm4/gpio.c
+++ b/chip/lm4/gpio.c
@@ -328,7 +328,7 @@ static void gpio_interrupt(int port, uint32_t mis)
 
 /**
  * Handlers for each GPIO port.  These read and clear the interrupt bits for
- * the port, then call the master handler above.
+ * the port, then call the controller handler above.
  */
 #define GPIO_IRQ_FUNC(irqfunc, gpiobase)		\
 	void irqfunc(void)				\
diff --git a/chip/lm4/lpc.c b/chip/lm4/lpc.c
index 0c672bd63a..8a59d6b434 100644
--- a/chip/lm4/lpc.c
+++ b/chip/lm4/lpc.c
@@ -759,16 +759,19 @@ static void lpc_init(void)
 #endif
 
 	/*
-	 * Ensure the EC (slave) has control of the memory-mapped I/O space.
-	 * Once the EC has won arbitration for the memory-mapped space, it will
-	 * keep control of it until it writes the last byte in the space.
-	 * (That never happens; we can't use the last byte in the space because
-	 * ACPI can't see it anyway.)
+	 * Ensure the EC (peripheral) has control of the memory-mapped I/O
+	 * space. Once the EC has won arbitration for the memory-mapped space,
+	 * it will keep control of it until it writes the last byte in the
+	 * space. (That never happens; we can't use the last byte in the space
+	 * because ACPI can't see it anyway.)
 	 */
 	while (!(LM4_LPC_ST(LPC_CH_MEMMAP) & 0x10)) {
 		/* Clear HW1ST */
 		LM4_LPC_ST(LPC_CH_MEMMAP) &= ~0x40;
-		/* Do a dummy slave write; this should cause SW1ST to be set */
+		/*
+		 * Do a dummy peripheral write; this should cause SW1ST to be
+		 * set.
+		 */
 		*LPC_POOL_MEMMAP = *LPC_POOL_MEMMAP;
 	}
 
diff --git a/common/ccd_config.c b/common/ccd_config.c
index 91232df295..f83789a26f 100644
--- a/common/ccd_config.c
+++ b/common/ccd_config.c
@@ -1459,7 +1459,7 @@ static enum vendor_cmd_rc ccd_vendor(struct vendor_cmd_params *p)
 	p->in_size++;
 
 	/*
-	 * Move response up for the master to see it in the right
+	 * Move response up for the controller to see it in the right
 	 * place in the response buffer.  We have to do this because the
 	 * first byte of the buffer on input was the subcommand, so we
 	 * passed buffer + 1 in the handler call above.
diff --git a/common/i2c_controller.c b/common/i2c_controller.c
index ac65483185..60d48e8b68 100644
--- a/common/i2c_controller.c
+++ b/common/i2c_controller.c
@@ -805,14 +805,14 @@ int i2c_unwedge(int port)
 
 	/*
 	 * If clock is low, wait for a while in case of clock stretched
-	 * by a slave.
+	 * by a peripheral.
 	 */
 	if (!i2c_raw_get_scl(port)) {
 		for (i = 0;; i++) {
 			if (i >= UNWEDGE_SCL_ATTEMPTS) {
 				/*
-				 * If we get here, a slave is holding the clock
-				 * low and there is nothing we can do.
+				 * If we get here, a peripheral is holding the
+				 * clock low and there is nothing we can do.
 				 */
 				CPRINTS("I2C%d unwedge failed, "
 					"SCL is held low", port);
@@ -837,9 +837,9 @@ int i2c_unwedge(int port)
 		udelay(I2C_BITBANG_DELAY_US);
 
 		/*
-		 * Clock through the problem by clocking out 9 bits. If slave
-		 * releases the SDA line, then we can stop clocking bits and
-		 * send a STOP.
+		 * Clock through the problem by clocking out 9 bits. If the
+		 * peripheral releases the SDA line, then we can stop clocking
+		 * bits and send a STOP.
 		 */
 		for (j = 0; j < 9; j++) {
 			if (i2c_raw_get_sda(port))
diff --git a/common/new_nvmem.c b/common/new_nvmem.c
index b7bb2b1c11..d3bfcb40b4 100644
--- a/common/new_nvmem.c
+++ b/common/new_nvmem.c
@@ -692,7 +692,7 @@ static enum ec_error_list set_first_page_header(void)
 	rv = write_to_flash(fph, &ph, sizeof(ph));
 
 	if (rv == EC_SUCCESS) {
-		/* Make sure master page tracker is ready. */
+		/* Make sure the controller page tracker is ready. */
 		memset(&controller_at, 0, sizeof(controller_at));
 		controller_at.mt.data_offset = ph.data_offset;
 		controller_at.mt.ph = fph;
diff --git a/common/tpm_registers.c b/common/tpm_registers.c
index b821df7f9a..185cadf97f 100644
--- a/common/tpm_registers.c
+++ b/common/tpm_registers.c
@@ -5,8 +5,8 @@
 
 /*
  * This implements the register interface for the TPM SPI Hardware Protocol.
- * The master puts or gets between 1 and 64 bytes to a register designated by a
- * 24-bit address. There is no provision for error reporting at this level.
+ * The controller puts or gets between 1 and 64 bytes to a register designated
+ * by a24-bit address. There is no provision for error reporting at this level.
  */
 
 #include "byteorder.h"
@@ -495,7 +495,7 @@ static void fifo_reg_read(uint8_t *dest, uint32_t data_size)
 		tpm_sts |= 63 << burst_count_shift;
 	} else {
 		/*
-		 * Tell the master how much there is to read in the next
+		 * Tell the controller how much there is to read in the next
 		 * burst.
 		 */
 		tpm_sts |= MIN(tpm_.fifo_write_index -
diff --git a/docs/ap-ec-comm.md b/docs/ap-ec-comm.md
index 0fc31b6822..27d5349ca4 100644
--- a/docs/ap-ec-comm.md
+++ b/docs/ap-ec-comm.md
@@ -112,15 +112,15 @@ the filler byte.
 ### SPI
 
 The SPI bus is similar to I<sup>2</sup>C, but with two major exceptions. First,
-there's a minimum speed on the SPI bus. If slave devices don't respond quickly
-enough, the master will assume they're broken and give up. Second, every
-transaction is bidirectional. When bits are being clocked from master to slave
-on the MOSI line, the master will simultaneously read bits in the other
-direction on the MISO line.
+there's a minimum speed on the SPI bus. If peripheral devices don't respond
+quickly enough, the controller will assume they're broken and give up. Second,
+every transaction is bidirectional. When bits are being clocked from controller
+to peripheral on the MOSI line, the controller will simultaneously read bits in
+the other direction on the MISO line.
 
 Hardware devices can usually handle this, and often some hardware-based flow
-control used to "stretch" the transaction by a bit or byte if the slave device
-needs a little extra time to respond to the master's demands.
+control used to "stretch" the transaction by a bit or byte if the peripheral
+device needs a little extra time to respond to the controller's demands.
 
 When exchanging messages with the EC on the SPI bus, the EC's host commands are
 communicated using our own software flow-control scheme, because most of the
diff --git a/docs/core_runtime.md b/docs/core_runtime.md
index 9d81b807be..680e5e4928 100644
--- a/docs/core_runtime.md
+++ b/docs/core_runtime.md
@@ -52,7 +52,7 @@ where you need to avoid it.
 The hardware interrupt requests are connected to the interruption handling
 *C* routines declared by the `DECLARE_IRQ` macros, through some chip/core
 specific mechanisms (e.g. depending whether we have a vectored interrupt
-controller, slave interrupt controllers...)
+controller, peripheral interrupt controllers...)
 
 The interrupts can be nested (ie interrupted by a higher priority interrupt).
 All the interrupt vectors are assigned a priority as defined in their
diff --git a/docs/ec_terms.md b/docs/ec_terms.md
index 3242302940..bd16635368 100644
--- a/docs/ec_terms.md
+++ b/docs/ec_terms.md
@@ -156,7 +156,7 @@
     Communication involves a SPI frame, consisting of the assertion of chip
     select, transmitting one or more bytes on the MOSI signal, receiving zero or
     more bytes on the MISO signal, and de-assertion of the chip select.  The
-    contents of a SPI frame varies based on the SPI slave type.
+    contents of a SPI frame varies based on the SPI peripheral type.
 
 *   **UART - Universal Asynchronous Receiver Transceiver**{#uart}
 
diff --git a/docs/usb_updater.md b/docs/usb_updater.md
index 476b50f316..cd4be9f881 100644
--- a/docs/usb_updater.md
+++ b/docs/usb_updater.md
@@ -44,7 +44,7 @@ will use `hammerd` (in `src/platform/hammerd`) to update the device.
 Update protocol
 ---------------
 
-The host (either a local AP or a workstation) is the master of the firmware
+The host (either a local AP or a workstation) is the controller of the firmware
 update protocol, it sends data to the Cr50 device, which processes it and
 responds.
 
diff --git a/include/config.h b/include/config.h
index 067ba0b9da..d37fd3ea41 100644
--- a/include/config.h
+++ b/include/config.h
@@ -2590,13 +2590,13 @@
 #undef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
 #undef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
 
-/* MCHP next two items are EC eSPI slave configuration */
-/* Maximum clock frequence eSPI EC slave advertises
+/* MCHP next two items are EC eSPI peripheral configuration */
+/* Maximum clock frequence eSPI EC peripheral advertises
  * Values in MHz are 20, 25, 33, 50, and 66
  */
 #undef CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ
 
-/* EC eSPI slave advertises IO lanes
+/* EC eSPI peripheral advertises IO lanes
  * 0 = Single
  * 1 = Single and Dual
  * 2 = Single and Quad
@@ -3138,17 +3138,19 @@
  */
 #undef CONFIG_SPI_NOR_SMART_ERASE
 
-/* SPI master feature */
+/* SPI controller feature */
 #undef CONFIG_SPI_CONTROLLER
 
-/* SPI master halfduplex/3-wire mode */
+/* SPI controller halfduplex/3-wire mode */
 #undef CONFIG_SPI_HALFDUPLEX
 
-/* SPI master configure gpios on init */
+/* SPI controller configure gpios on init */
 #undef CONFIG_SPI_CONTROLLER_CONFIGURE_GPIOS
 
-/* Support SPI masters without GPIO-specified Chip Selects, instead rely on the
- * SPI master port's hardwired CS pin. */
+/*
+ * Support SPI controller's without GPIO-specified Chip Selects, instead rely on
+ * the SPI controller port's hardwired CS pin.
+ */
 #undef CONFIG_SPI_CONTROLLER_NO_CS_GPIOS
 
 /* Support testing SPI periph interface driver. */
diff --git a/include/spi.h b/include/spi.h
index c42b7ab757..10286accab 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -30,7 +30,7 @@ enum spi_clock_mode {
 struct spi_device_t {
 	/*
 	 * SPI port the device is connected to.
-	 * On some architecture, this is SPI master port index,
+	 * On some architecture, this is SPI controller port index,
 	 * on other the SPI port index directly.
 	 */
 	uint8_t port;
diff --git a/include/spi_nor.h b/include/spi_nor.h
index 173da85012..d56d26802c 100644
--- a/include/spi_nor.h
+++ b/include/spi_nor.h
@@ -41,7 +41,7 @@ struct spi_nor_device_t {
 	/* Name of the Serial NOR Flash device. */
 	const char *name;
 
-	/* Index of the SPI master which this device is connected through. */
+	/* Index of the SPI controller this device is connected through. */
 	const enum spi_device spi_controller;
 
 	/* Maximum timeout per command in microseconds. */
@@ -109,9 +109,9 @@ int spi_nor_init(void);
  *
  * WARNING:
  * 1) In 3 Byte addressing mode only 16MiB of Serial NOR Flash is accessible.
- * 2) If there's a second SPI master communicating with this Serial NOR Flash
- *    part on the board, the user is responsible for ensuring addressing mode
- *    compatibility and cooperation.
+ * 2) If there's a second SPI controller communicating with this Serial NOR
+ *    Flash part on the board, the user is responsible for ensuring addressing
+ *    mode compatibility and cooperation.
  * 3) The user must ensure that multiple users do not trample on each other
  *    by having multiple parties changing the device's addressing mode.
  *
diff --git a/include/test_util.h b/include/test_util.h
index 21ea21595b..4f98d29a6e 100644
--- a/include/test_util.h
+++ b/include/test_util.h
@@ -268,7 +268,7 @@ struct test_i2c_write_dev {
  *
  * When this function is called, it should either perform the desired
  * mock functionality, or return EC_ERROR_INVAL to indicate it does
- * not respond to the specified port and slave address.
+ * not respond to the specified port and peripheral address.
  *
  * @param routine     Function pointer, with the same prototype as i2c_xfer()
  */
@@ -280,7 +280,7 @@ struct test_i2c_write_dev {
 
 /*
  * Detach an I2C device. Once detached, any read/write command regarding the
- * specified port and slave address returns error.
+ * specified port and peripheral address returns error.
  *
  * @param port       The port that the detached device is connected to
  * @param periph_addr The address of the detached device
diff --git a/include/tpm_registers.h b/include/tpm_registers.h
index d02bc9e276..d35824dfce 100644
--- a/include/tpm_registers.h
+++ b/include/tpm_registers.h
@@ -5,8 +5,8 @@
 
 /*
  * This defines the interface functions for TPM SPI Hardware Protocol. The SPI
- * master reads or writes between 1 and 64 bytes to a register designated by a
- * 24-bit address. There is no provision for error reporting at this level.
+ * controller reads or writes between 1 and 64 bytes to a register designated by
+ * a 24-bit address. There is no provision for error reporting at this level.
  */
 
 #ifndef __CROS_EC_TPM_REGISTERS_H
@@ -16,11 +16,11 @@
 
 #include "common.h"
 
-/* The SPI master is writing data into a TPM register. */
+/* The SPI controller is writing data into a TPM register. */
 void tpm_register_put(uint32_t regaddr,
 		      const uint8_t *data, uint32_t data_size);
 
-/* The SPI master is reading data from a TPM register. */
+/* The SPI controller is reading data from a TPM register. */
 void tpm_register_get(uint32_t regaddr, uint8_t *dest, uint32_t data_size);
 
 /* Get the current value of the burst size field of the status register. */
diff --git a/test/tpm_test/ftdi_spi_tpm.c b/test/tpm_test/ftdi_spi_tpm.c
index ebec39b766..22e287af5e 100644
--- a/test/tpm_test/ftdi_spi_tpm.c
+++ b/test/tpm_test/ftdi_spi_tpm.c
@@ -99,7 +99,7 @@ static void StartTransaction(int read_write, size_t bytes, unsigned addr)
 	char *transfer_data;
 
 	/*
-	 * give it 10 ms. TODO(vbendeb): remove this once cr50 SPS TPM driver
+	 * give it 10 ms. TODO(vbendeb): remove this once cr50 SPP TPM driver
 	 * performance is fixed.
 	 */
 	usleep(10000);
@@ -124,12 +124,13 @@ static void StartTransaction(int read_write, size_t bytes, unsigned addr)
 	 * control (Section "6.4.5 Flow Control" of the TCG issued "TPM
 	 * Profile (PTP) Specification Revision 00.43).
 	 *
-	 * The slave (TPM device) expects each transaction to start with a 4
-	 * byte header trasmitted by master. If the slave needs to stall the
-	 * transaction, it sets the MOSI bit to 0 during the last clock of the
-	 * 4 byte header. In this case the master is supposed to start polling
-	 * the line, byte at time, until the last bit in the received byte
-	 * (transferred during the last clock of the byte) is set to 1.
+	 * The peripheral (TPM device) expects each transaction to start with a
+	 * 4 byte header trasmitted by controller. If the peripheral needs to
+	 * stall the transaction, it sets the MOSI bit to 0 during the last
+	 * clock of the 4 byte header. In this case the controller is supposed
+	 * to start polling the line, byte at time, until the last bit in the
+	 * received byte (transferred during the last clock of the byte) is set
+	 * to 1.
 	 */
 	flow_c = transfer_data[3];
 	free(transfer_data);