diff options
author | Keith Short <keithshort@chromium.org> | 2020-02-14 14:31:18 -0700 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2020-02-26 01:04:51 +0000 |
commit | ff6cbc138b6ed692fcbae21bd9bf12837c2aeb79 (patch) | |
tree | 4ec732a06ca8582ca419e893e7030fb0c2134c61 | |
parent | 2696c706b8b97f28dfc5448687f168e9225cc61f (diff) | |
download | chrome-ec-stabilize-volteer-12931.B-master.tar.gz |
volteer: Update USB C1 reset for next buildstabilize-volteer-12931.B-master
Update the GPIO assignment for the USB_C1_RT_RST_ODL signal for the next
board build.
BUG=b:144933528, b:148243971
BRANCH=none
TEST=make buildall
TEST=Check unassigned board ID or board ID=0 uses legacy GPIO setting.
Otherwise new GPIO setting is used.
Change-Id: I4621e039e4461a4e10ab87bc2d4e000b5dcaa885
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2057496
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
-rw-r--r-- | baseboard/volteer/baseboard.c | 24 | ||||
-rw-r--r-- | baseboard/volteer/baseboard.h | 1 | ||||
-rw-r--r-- | board/volteer/gpio.inc | 12 | ||||
-rw-r--r-- | driver/retimer/bb_retimer.h | 13 | ||||
-rw-r--r-- | include/config.h | 3 |
5 files changed, 43 insertions, 10 deletions
diff --git a/baseboard/volteer/baseboard.c b/baseboard/volteer/baseboard.c index c9e7543ad3..207a6c0491 100644 --- a/baseboard/volteer/baseboard.c +++ b/baseboard/volteer/baseboard.c @@ -407,7 +407,7 @@ struct usb_mux usb_muxes[] = { }; BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT); -const struct bb_usb_control bb_controls[] = { +struct bb_usb_control bb_controls[] = { [USBC_PORT_C0] = { /* USB-C port 0 doesn't have a retimer */ }, @@ -468,14 +468,16 @@ void ppc_interrupt(enum gpio_signal signal) /******************************************************************************/ /* TCPC support routines */ +static enum gpio_signal ps8xxx_rst_odl = GPIO_USB_C1_RT_RST_ODL; + static void ps8815_reset(void) { int val; - gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0); + gpio_set_level(ps8xxx_rst_odl, 0); msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS)); - gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1); + gpio_set_level(ps8xxx_rst_odl, 1); msleep(PS8815_FW_INIT_DELAY_MS); /* @@ -661,6 +663,20 @@ static void config_db_usb3(void) sizeof(usb_retimers[USBC_PORT_C1])); } +/* + * Reconfigure Volteer GPIOs based on the board ID + */ +static void config_volteer_gpios(void) +{ + /* Legacy support for the first board build */ + if (get_board_id() == 0) { + /* Reassign USB_C1_RT_RST_ODL */ + bb_controls[USBC_PORT_C1].retimer_rst_gpio = + GPIO_USB_C1_RT_RST_ODL_BOARDID_0; + ps8xxx_rst_odl = GPIO_USB_C1_RT_RST_ODL_BOARDID_0; + } +} + static uint8_t board_id; uint8_t get_board_id(void) @@ -688,6 +704,8 @@ static void cbi_init(void) CPRINTS("Board ID: %d", board_id); + config_volteer_gpios(); + /* FW config */ if (cbi_get_fw_config(&cbi_val) != EC_SUCCESS) { diff --git a/baseboard/volteer/baseboard.h b/baseboard/volteer/baseboard.h index 7fd84e7acf..9be9e208fb 100644 --- a/baseboard/volteer/baseboard.h +++ b/baseboard/volteer/baseboard.h @@ -225,6 +225,7 @@ /* Retimer */ #define CONFIG_USBC_MUX_RETIMER #define CONFIG_USBC_RETIMER_INTEL_BB +#define CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG #define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x40 /* diff --git a/board/volteer/gpio.inc b/board/volteer/gpio.inc index d4cbfcaa47..02a63c98f0 100644 --- a/board/volteer/gpio.inc +++ b/board/volteer/gpio.inc @@ -61,7 +61,6 @@ UNIMPLEMENTED(PCH_DSW_PWROK) GPIO(EN_DRAM_VDDQ, PIN(F, 2), GPIO_OUT_LOW) GPIO(EN_PP1050_STG, PIN(C, 0), GPIO_OUT_LOW) GPIO(EN_PP5000_USB_AG, PIN(A, 7), GPIO_OUT_LOW) -GPIO(EN_PP1800_A, PIN(8, 3), GPIO_OUT_LOW) GPIO(EN_PPVAR_VCCIN_AUX, PIN(8, 1), GPIO_OUT_LOW) GPIO(EN_PP1050_ST_S0, PIN(3, 4), GPIO_OUT_LOW) GPIO(EN_VNN_BYPASS, PIN(B, 0), GPIO_OUT_LOW) @@ -95,8 +94,15 @@ GPIO(EC_PCH_INT_ODL, PIN(D, 6), GPIO_ODR_HIGH) /* TODO - b/140557015 - /* USB and USBC Signals */ -/* TODO(b/148243971): update PIN for next build */ -GPIO(USB_C1_RT_RST_ODL, PIN(3, 2), GPIO_ODR_LOW) /* USB_C1 Reset */ +/* + * USB_C1 moved from GPIO32 to GPIO83 on boards with board ID >=1. + * GPIO83/EN_PP1800_A is DNS on board ID 0 and GPIO32 is N/C on board ID >=1 + * so it's safe to define GPIOs compatible with both designs. + * TODO (b/149858568): remove board ID=0 support. + */ +GPIO(USB_C1_RT_RST_ODL_BOARDID_0, PIN(3, 2), GPIO_ODR_LOW) /* USB_C1 Reset on boards without board ID */ +GPIO(USB_C1_RT_RST_ODL, PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset on boards board ID >=1 */ + /* Don't have a load switch for retimer */ UNIMPLEMENTED(USB_C1_LS_EN) /* Retimer Force Power enable is connected to AP */ diff --git a/driver/retimer/bb_retimer.h b/driver/retimer/bb_retimer.h index 4ca3b49f8f..3b34b72e3d 100644 --- a/driver/retimer/bb_retimer.h +++ b/driver/retimer/bb_retimer.h @@ -45,14 +45,19 @@ extern const struct usb_retimer_driver bb_usb_retimer; /* Retimer driver hardware specific controls */ struct bb_usb_control { /* NVM flag if shared with multiple retimers */ - const bool shared_nvm; + bool shared_nvm; /* Load switch enable */ - const enum gpio_signal usb_ls_en_gpio; + enum gpio_signal usb_ls_en_gpio; /* Retimer reset */ - const enum gpio_signal retimer_rst_gpio; + enum gpio_signal retimer_rst_gpio; /* Force power (active/low) */ - const enum gpio_signal force_power_gpio; + enum gpio_signal force_power_gpio; }; + +#ifndef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG extern const struct bb_usb_control bb_controls[]; +#else +extern struct bb_usb_control bb_controls[]; +#endif #endif /* __CROS_EC_BB_RETIMER_H */ diff --git a/include/config.h b/include/config.h index 0d5ad579e3..b289658130 100644 --- a/include/config.h +++ b/include/config.h @@ -3987,6 +3987,9 @@ #undef CONFIG_USBC_RETIMER_PS8818 #undef CONFIG_USBC_RETIMER_TUSB544 +/* Allow run-time configuration of the Burnside Bridge driver structure */ +#undef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG + /* * Adds an EC console command to erase the ANX7447 OCM flash. * Note: this is intended to be a temporary option and |