diff options
| author | Scott <scollyer@chromium.org> | 2016-10-21 11:47:40 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-10-26 01:45:29 -0700 |
| commit | 450b944ca98166a05c13adabefe97a26f9ebc382 (patch) | |
| tree | 289e9a4f01a2f18528b5f8977ae156f398fc7075 | |
| parent | 907c09ee381ed53c7b081379ba71ed69fb062293 (diff) | |
| download | chrome-ec-450b944ca98166a05c13adabefe97a26f9ebc382.tar.gz | |
Cr50: i2cs: Re-enable sleep after every interrupt
Previously, sleep was being reenabled only after tpm fifo reads as
that would typcially be near the end of a host driven TPM
command. However, in the case the host reads or writes to the STS
register, then sleep would not be re-enabled. Moved the re-enable
point to at the end of every i2cs interrupt. Since sleep is delayed by
1 second prior to being reenabled then Cr50 will not go to sleep in
the middle of TPM command since the host is either writing or reading
STS at a much faster rate when a TPM command is being executed.
BRANCH=none
BUG=chrome-os-partner:40397
TEST=manual
Added a debug counter in idle.c and shortened sleep delays from 3
minutes to 5 seconds. Unplugged suzyq and verified that when
reconnected, the counter was incrementing to verify that Reef would
go to sleep. Also verified that TPM worked successfully and kernel
was launched.
Change-Id: I03ad33ed3591bbba24b5c56445c06d0e11368019
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/401808
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
| -rw-r--r-- | chip/g/i2cs.c | 8 | ||||
| -rw-r--r-- | common/i2cs_tpm.c | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/chip/g/i2cs.c b/chip/g/i2cs.c index 7cced88fcc..5c54af9d9d 100644 --- a/chip/g/i2cs.c +++ b/chip/g/i2cs.c @@ -186,6 +186,14 @@ static void _i2cs_write_complete_int(void) /* Invoke the callback to process the message. */ write_complete_handler_(i2cs_buffer, bytes_processed); } + + /* + * Could be the end of a TPM trasaction. Set sleep to be reenabled in 1 + * second. If this is not the end of a TPM response, then sleep will be + * disabled again in the next I2CS interrupt. + */ + delay_sleep_by(1 * SECOND); + enable_sleep(SLEEP_MASK_I2C_SLAVE); } DECLARE_IRQ(GC_IRQNUM_I2CS0_INTR_WRITE_COMPLETE_INT, _i2cs_write_complete_int, 1); diff --git a/common/i2cs_tpm.c b/common/i2cs_tpm.c index 5aa3a07e01..9b41f3c9ec 100644 --- a/common/i2cs_tpm.c +++ b/common/i2cs_tpm.c @@ -130,14 +130,6 @@ static void process_read_access(uint16_t reg_size, tpm_register_get(tpm_reg, data, reg_size); /* Transfer TPM fifo data to the I2CS HW fifo */ i2cs_post_read_fill_fifo(data, reg_size); - - /* - * Could be the end of a TPM trasaction. Set sleep to be reenabled in 1 - * second. If this is not the end of a TPM response, then sleep will be - * disabled again in the next I2CS interrupt. - */ - delay_sleep_by(1 * SECOND); - enable_sleep(SLEEP_MASK_I2C_SLAVE); } static void process_write_access(uint16_t reg_size, uint16_t tpm_reg, |