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| author | Mulin Chao <mlchao@nuvoton.com> | 2016-06-14 14:22:21 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-06-14 22:00:53 -0700 |
| commit | 4bb0efcc28d5c13721867f0bca1bfd3db68268b4 (patch) | |
| tree | 131dfcd8b9551c01be9b4ec71807d9b800761ffb | |
| parent | aff5c83053cf88edf3c4331b09b25d7361c1ba9a (diff) | |
| download | chrome-ec-4bb0efcc28d5c13721867f0bca1bfd3db68268b4.tar.gz | |
npcx: Fixed host access pending bit issue in INT11 ISR.
Since the pending bit of host access interrupt is set frequently if
PCH accesses KBC/PM_Channel/Shared Memory through LPC after entering
S0. It's better to add checking enable bit of MIWU of it in case huge
latency between gpio interrupt and serving its own ISR in INT11's ISR.
Modified sources:
1. gpio.c: Add checking enable bit of MIWU of host access in INT11 ISR.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
Change-Id: I1ae57173eb208fa78218bc01cfbc91f9a29c5c81
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/352362
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
| -rw-r--r-- | chip/npcx/gpio.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c index 5b9c0ec417..fb95f101f1 100644 --- a/chip/npcx/gpio.c +++ b/chip/npcx/gpio.c @@ -788,16 +788,16 @@ void __gpio_wk0efgh_interrupt(void) { #ifdef CONFIG_LPC /* Pending bit 7 or 6 ? */ - if (NPCX_WKPND(MIWU_TABLE_0 , MIWU_GROUP_5) & 0xC0) { - if (IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0 , MIWU_GROUP_5), 6)) { - /* Clear pending bit of WUI */ - SET_BIT(NPCX_WKPCL(MIWU_TABLE_0 , MIWU_GROUP_5), 6); - /* Disable host wake-up */ - CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6); - } - if (IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0 , MIWU_GROUP_5), 7)) - lpc_lreset_pltrst_handler(); - } else + if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0 , MIWU_GROUP_5), 6) && + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0 , MIWU_GROUP_5), 6)) { + /* Disable host wake-up */ + CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6); + /* Clear pending bit of WUI */ + SET_BIT(NPCX_WKPCL(MIWU_TABLE_0 , MIWU_GROUP_5), 6); + } else if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0 , MIWU_GROUP_5), 7) && + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0 , MIWU_GROUP_5), 7)) + lpc_lreset_pltrst_handler(); + else /* FW will jump into ISR again if other GPIOs' INT still issued */ #endif gpio_interrupt(NPCX_IRQ_WKINTEFGH_0); } |