Zephyr: npcx: shim SHI

BUG=b:182600858
BRANCH=none
TEST=Test host command "version" and "Hello" on npcx7_evb and the host
emulator.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: Ie9424d9e68a04f575bc6f695b29ca64f14147eef
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2786888
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: Jack Rosenthal <jrosenth@chromium.org>

2 files changed, 86 insertions, 0 deletions

diff --git a/zephyr/shim/chip/npcx/CMakeLists.txt b/zephyr/shim/chip/npcx/CMakeLists.txt
index 93732b9154..39a56170d4 100644
--- a/zephyr/shim/chip/npcx/CMakeLists.txt
+++ b/zephyr/shim/chip/npcx/CMakeLists.txt
@@ -6,6 +6,7 @@ zephyr_library_include_directories(include)
 
 zephyr_library_sources(clock.c)
 zephyr_library_sources_ifdef(CONFIG_CROS_KB_RAW_NPCX  keyboard_raw.c)
+zephyr_library_sources_ifdef(CONFIG_CROS_SHI_NPCX     shi.c)
 zephyr_library_sources_ifdef(CONFIG_CROS_EC           system.c)
 
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_EXTERNAL_STORAGE
diff --git a/zephyr/shim/chip/npcx/shi.c b/zephyr/shim/chip/npcx/shi.c
new file mode 100644
index 0000000000..d47f8d2ae7
--- /dev/null
+++ b/zephyr/shim/chip/npcx/shi.c
@@ -0,0 +1,85 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Functions needed by Serial Host Interface module for Chrome EC */
+
+#include <device.h>
+#include <dt-bindings/clock/npcx_clock.h>
+#include <logging/log.h>
+#include <soc.h>
+#include <zephyr.h>
+
+#include "chipset.h"
+#include "drivers/cros_shi.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "system.h"
+
+LOG_MODULE_REGISTER(shim_cros_shi, LOG_LEVEL_DBG);
+
+#define CROS_SHI_DEV DT_LABEL(DT_NODELABEL(shi))
+
+static void shi_enable(void)
+{
+	const struct device *cros_shi_dev = device_get_binding(CROS_SHI_DEV);
+	if (!cros_shi_dev) {
+		LOG_ERR("Fail to bind %s device", CROS_SHI_DEV);
+		return;
+	}
+
+	LOG_INF("%s", __func__);
+	cros_shi_enable(cros_shi_dev);
+}
+#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
+DECLARE_HOOK(HOOK_CHIPSET_RESUME_INIT, shi_enable, HOOK_PRIO_DEFAULT);
+#else
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, shi_enable, HOOK_PRIO_DEFAULT);
+#endif
+
+static void shi_reenable_on_sysjump(void)
+{
+	if (IS_ENABLED(CONFIG_CROS_SHI_NPCX_DEBUG) && system_jumped_late() &&
+	    chipset_in_state(CHIPSET_STATE_ON)) {
+		shi_enable();
+	}
+}
+/* Call hook after chipset sets initial power state */
+DECLARE_HOOK(HOOK_INIT, shi_reenable_on_sysjump, HOOK_PRIO_INIT_CHIPSET + 1);
+
+static void shi_disable(void)
+{
+	const struct device *cros_shi_dev = device_get_binding(CROS_SHI_DEV);
+	if (!cros_shi_dev) {
+		LOG_ERR("Fail to bind %s device", CROS_SHI_DEV);
+		return;
+	}
+
+	LOG_INF("%s", __func__);
+	cros_shi_disable(cros_shi_dev);
+}
+#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND_COMPLETE, shi_disable, HOOK_PRIO_DEFAULT);
+#else
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, shi_disable, HOOK_PRIO_DEFAULT);
+#endif
+DECLARE_HOOK(HOOK_SYSJUMP, shi_disable, HOOK_PRIO_DEFAULT);
+
+/* Get protocol information */
+static enum ec_status shi_get_protocol_info(struct host_cmd_handler_args *args)
+{
+	struct ec_response_get_protocol_info *r = args->response;
+
+	memset(r, '\0', sizeof(*r));
+	r->protocol_versions = BIT(3);
+	r->max_request_packet_size = CONFIG_CROS_SHI_MAX_REQUEST;
+	r->max_response_packet_size = CONFIG_CROS_SHI_MAX_RESPONSE;
+	r->flags = EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED;
+
+	args->response_size = sizeof(*r);
+
+	return EC_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, shi_get_protocol_info,
+		     EC_VER_MASK(0));