diff options
author | Jett Rink <jettrink@chromium.org> | 2018-03-05 12:49:31 -0700 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2018-03-08 14:04:39 -0800 |
commit | 700523f49753637ebe744303f0e611c999fcfd8d (patch) | |
tree | f36084cdc36bb965f51e27eb5d30ff7b0dce32e1 | |
parent | 0edf807724d647550cdb6818eb0893d8517fbe8e (diff) | |
download | chrome-ec-700523f49753637ebe744303f0e611c999fcfd8d.tar.gz |
yorp: Implement initial power sequence for chipset.
Also adding eSPI define.
BRANCH=none
BUG=b:74020444,b:74018816
TEST=none
Change-Id: Id237de92ed1276213b60b61968e2fc59817e0aa7
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/949722
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
-rw-r--r-- | board/yorp/board.c | 61 | ||||
-rw-r--r-- | board/yorp/board.h | 31 | ||||
-rw-r--r-- | board/yorp/ec.tasklist | 4 | ||||
-rw-r--r-- | board/yorp/gpio.inc | 46 |
4 files changed, 134 insertions, 8 deletions
diff --git a/board/yorp/board.c b/board/yorp/board.c index b44483a0e1..ad811e0fae 100644 --- a/board/yorp/board.c +++ b/board/yorp/board.c @@ -6,17 +6,72 @@ /* Yorp board-specific configuration */ #include "common.h" +#include "extpower.h" #include "gpio.h" +#include "hooks.h" #include "lid_switch.h" +#include "power.h" #include "power_button.h" #include "switch.h" #include "system.h" #include "util.h" -#include "gpio_list.h" /* Must come after other header files. */ +/* Must come after other header files. */ +#include "gpio_list.h" -/* TODO(b/73811887): Fill out correctly */ const enum gpio_signal hibernate_wake_pins[] = { - GPIO_LID_OPEN + GPIO_LID_OPEN, + GPIO_AC_PRESENT, + GPIO_POWER_BUTTON_L }; const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); + + +/* Power signal list. Must match order of enum power_signal. */ +const struct power_signal_info power_signal_list[] = { +#ifdef CONFIG_POWER_S0IX + {GPIO_PCH_SLP_S0_L, + POWER_SIGNAL_ACTIVE_HIGH | POWER_SIGNAL_DISABLE_AT_BOOT, + "SLP_S0_DEASSERTED"}, +#endif + {GPIO_PCH_SLP_S3_L, POWER_SIGNAL_ACTIVE_HIGH, "SLP_S3_DEASSERTED"}, + {GPIO_PCH_SLP_S4_L, POWER_SIGNAL_ACTIVE_HIGH, "SLP_S4_DEASSERTED"}, + {GPIO_SUSPWRDNACK, POWER_SIGNAL_ACTIVE_HIGH, + "SUSPWRDNACK_DEASSERTED"}, + + {GPIO_ALL_SYS_PGOOD, POWER_SIGNAL_ACTIVE_HIGH, "ALL_SYS_PGOOD"}, + {GPIO_RSMRST_L_PGOOD, POWER_SIGNAL_ACTIVE_HIGH, "RSMRST_L"}, + {GPIO_PP3300_PG, POWER_SIGNAL_ACTIVE_HIGH, "PP3300_PG"}, + {GPIO_PP5000_PG, POWER_SIGNAL_ACTIVE_HIGH, "PP5000_PG"}, +}; +BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); + + +/* Called by APL power state machine when transitioning from G3 to S5 */ +static void chipset_pre_init(void) +{ + /* Enable 5.0V and 3.3V rails, and wait for Power Good */ + gpio_set_level(GPIO_EN_PP5000, 1); + gpio_set_level(GPIO_EN_PP3300, 1); + while (!gpio_get_level(GPIO_PP5000_PG) || + !gpio_get_level(GPIO_PP3300_PG)) + ; + + /* Enable PMIC */ + gpio_set_level(GPIO_PMIC_EN, 1); +} +DECLARE_HOOK(HOOK_CHIPSET_PRE_INIT, chipset_pre_init, HOOK_PRIO_DEFAULT); + +/* Called by APL power state machine when transitioning to G3. */ +void chipset_do_shutdown(void) +{ + /* Disable PMIC */ + gpio_set_level(GPIO_PMIC_EN, 0); + + /* Disable 5.0V and 3.3V rails, and wait until they power down. */ + gpio_set_level(GPIO_EN_PP5000, 0); + gpio_set_level(GPIO_EN_PP3300, 0); + while (gpio_get_level(GPIO_PP5000_PG) || + gpio_get_level(GPIO_PP3300_PG)) + ; +} diff --git a/board/yorp/board.h b/board/yorp/board.h index 191085aab5..4ea05c4676 100644 --- a/board/yorp/board.h +++ b/board/yorp/board.h @@ -23,7 +23,21 @@ #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q128 /* Internal SPI flash type. */ +/* SoC / PCH */ +/* GEMINILAKE reuses apollo lake power seq */ +#define CONFIG_CHIPSET_APOLLOLAKE +#define CONFIG_CHIPSET_RESET_HOOK +#define CONFIG_ESPI +/* TODO(b/74123961): Enable Virtual Wires after bringup */ +#define CONFIG_LPC +#define CONFIG_POWER_COMMON +#define CONFIG_POWER_S0IX +#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE #define CONFIG_POWER_BUTTON +#define CONFIG_POWER_BUTTON_X86 +#define CONFIG_EXTPOWER_GPIO +/* TODO(b/73811887), increase CONFIG_EXTPOWER_DEBOUNCE_MS from 30 to 1000? */ + #ifndef __ASSEMBLER__ @@ -35,6 +49,23 @@ enum adc_channel { ADC_CH_COUNT }; +enum power_signal { +#ifdef CONFIG_POWER_S0IX + X86_SLP_S0_N, /* PCH -> SLP_S0_L */ +#endif + X86_SLP_S3_N, /* PCH -> SLP_S3_L */ + X86_SLP_S4_N, /* PCH -> SLP_S4_L */ + X86_SUSPWRDNACK, /* PCH -> SUSPWRDNACK */ + + X86_ALL_SYS_PG, /* PMIC -> PMIC_EC_PWROK_OD */ + X86_RSMRST_N, /* PMIC -> PMIC_EC_RSMRST_ODL */ + X86_PGOOD_PP3300, /* PMIC -> PP3300_PG_OD */ + X86_PGOOD_PP5000, /* PMIC -> PP5000_PG_OD */ + + /* Number of X86 signals */ + POWER_SIGNAL_COUNT +}; + #endif /* !__ASSEMBLER__ */ #endif /* __CROS_EC_BOARD_H */ diff --git a/board/yorp/ec.tasklist b/board/yorp/ec.tasklist index c4cbb43a33..d0032f5d7d 100644 --- a/board/yorp/ec.tasklist +++ b/board/yorp/ec.tasklist @@ -22,5 +22,7 @@ #define CONFIG_TASK_LIST \ TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \ TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \ - TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) + TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) diff --git a/board/yorp/gpio.inc b/board/yorp/gpio.inc index c937d02c36..07c51c97e4 100644 --- a/board/yorp/gpio.inc +++ b/board/yorp/gpio.inc @@ -7,9 +7,47 @@ /* Declare symbolic names for all the GPIOs that we care about. * Note: Those with interrupt handlers must be declared first. */ -GPIO_INT(LID_OPEN, PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt) -GPIO_INT(WP_L, PIN(A, 1), GPIO_INT_BOTH, switch_interrupt) -GPIO_INT(POWER_BUTTON_L, PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt) +GPIO_INT(LID_OPEN, PIN(D, 2), GPIO_INT_BOTH | + GPIO_HIB_WAKE_HIGH, lid_interrupt) +GPIO_INT(WP_L, PIN(A, 1), GPIO_INT_BOTH, switch_interrupt) /* EC_WP_ODL */ +GPIO_INT(POWER_BUTTON_L, PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt) /* EC_PWR_BTN_ODL */ +#ifdef CONFIG_POWER_S0IX +GPIO_INT(PCH_SLP_S0_L, PIN(A, 4), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S0_L */ +#endif +GPIO_INT(PCH_SLP_S4_L, PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S4_L */ +GPIO_INT(PCH_SLP_S3_L, PIN(A, 6), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S3_L */ +GPIO_INT(SUSPWRDNACK, PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt) /* SUSPWRDNACK */ +GPIO_INT(RSMRST_L_PGOOD, PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt) /* PMIC_EC_RSMRST_ODL */ +GPIO_INT(ALL_SYS_PGOOD, PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt) /* PMIC_EC_PWROK_OD */ +GPIO_INT(AC_PRESENT, PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt) /* ACOK_OD */ -GPIO(ENTERING_RW, PIN(8, 0), GPIO_OUT_LOW) /* EC Entering RW */
\ No newline at end of file +/* Define PCH_SLP_S0_L after all interrupts if CONFIG_POWER_S0IX not defined. */ +#ifndef CONFIG_POWER_S0IX +GPIO(PCH_SLP_S0_L, PIN(A, 4), GPIO_INPUT) /* SLP_S0_L */ +#endif + +/* + * TODO(b/74123961): Move PLT_RST_L and PCH_RCIN_L to virtual wires over eSPI + */ +GPIO(PLT_RST_L, PIN(C, 7), GPIO_INPUT) /* Platform Reset from SoC */ +GPIO(PCH_RCIN_L, PIN(0, 2), GPIO_ODR_HIGH) /* SYS_RST_ODL */ + +GPIO(ENTERING_RW, PIN(8, 0), GPIO_OUT_LOW) /* EC_ENTERING_RW */ +GPIO(PCH_WAKE_L, PIN(7, 4), GPIO_ODR_HIGH) /* EC_PCH_WAKE_ODL */ +GPIO(PCH_PWRBTN_L, PIN(C, 1), GPIO_ODR_HIGH) /* GPIO_PCH_PWRBTN_L */ + +GPIO(EN_PP5000, PIN(7, 3), GPIO_OUT_LOW) /* EN_PP5000_A */ +GPIO(PP5000_PG, PIN(C, 0), GPIO_INPUT) /* PP5000_PG_OD */ +GPIO(EN_PP3300, PIN(D, 4), GPIO_OUT_LOW) /* EN_PP3300_A */ +GPIO(PP3300_PG, PIN(6, 0), GPIO_INPUT) /* PP3300_PG_OD */ +GPIO(PMIC_EN, PIN(D, 7), GPIO_OUT_LOW) /* Enable A Rails via PMIC */ +GPIO(PCH_RSMRST_L, PIN(C, 2), GPIO_OUT_LOW) /* RSMRST# to SOC. All _A rails now up. */ +GPIO(PCH_SYS_PWROK, PIN(B, 7), GPIO_OUT_LOW) /* EC_PCH_PWROK. All S0 rails now up. */ + +/* + * PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is + * normally driven by the PMIC. The EC can also drive this signal in the event + * that the ambient or charger temperature sensors exceeds their thresholds. + */ +GPIO(CPU_PROCHOT, PIN(3, 7), GPIO_INPUT | GPIO_SEL_1P8V) /* PCH_PROCHOT_ODL */
\ No newline at end of file |