diff options
author | Vincent Palatin <vpalatin@chromium.org> | 2018-04-26 12:43:14 +0200 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2018-06-04 10:09:41 -0700 |
commit | 87387cc741a24805315419106dcf2c1ecdc1111a (patch) | |
tree | 1c56914e41f142c3e892519fe4e63252e0bb5415 | |
parent | 4a0bd0cedab55f119419b0a8c70ca05d47b4a8e2 (diff) | |
download | chrome-ec-87387cc741a24805315419106dcf2c1ecdc1111a.tar.gz |
meowth_fp: update AP interrupt configuration
Set the GPIO output driving the PCH interrupt as push-pull as the other
side has a 100K pull-down.
No longer modify the GPIO config in S3, the PCH doesn't seem to work
this way, but needs to be confirmed.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=poppy
BUG=b:78613978
TEST=On Meowth, monitor /proc/interrupts before and after suspend/resume
cycle, no more interrupt storm on Int 46 / chromeos-ec.
Change-Id: I6198412d791ed9810ffa208fffbb8f378421decd
Reviewed-on: https://chromium-review.googlesource.com/1032775
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
-rw-r--r-- | board/meowth_fp/board.c | 2 | ||||
-rw-r--r-- | board/meowth_fp/gpio.inc | 2 |
2 files changed, 1 insertions, 3 deletions
diff --git a/board/meowth_fp/board.c b/board/meowth_fp/board.c index ad6748065d..071c517d2a 100644 --- a/board/meowth_fp/board.c +++ b/board/meowth_fp/board.c @@ -30,10 +30,8 @@ static void ap_deferred(void) && gpio_get_level(GPIO_PCH_SLP_S0_L); if (running) { /* S0 */ - gpio_set_flags(GPIO_EC_INT_L, GPIO_ODR_HIGH | GPIO_PULL_UP); hook_notify(HOOK_CHIPSET_RESUME); } else { /* S3 */ - gpio_set_flags(GPIO_EC_INT_L, GPIO_INPUT); hook_notify(HOOK_CHIPSET_SUSPEND); } } diff --git a/board/meowth_fp/gpio.inc b/board/meowth_fp/gpio.inc index a303868af6..e0470b2cb6 100644 --- a/board/meowth_fp/gpio.inc +++ b/board/meowth_fp/gpio.inc @@ -16,7 +16,7 @@ GPIO(PCH_SLP_SUS_L, PIN(D, 3), GPIO_INPUT) GPIO(WP, PIN(B, 7), GPIO_INPUT) /* Outputs */ -GPIO(EC_INT_L, PIN(A, 1), GPIO_INPUT) /* Enabled when PCH is up */ +GPIO(EC_INT_L, PIN(A, 1), GPIO_OUT_HIGH) GPIO(FP_RST_ODL, PIN(E, 0), GPIO_OUT_HIGH) GPIO(SPI4_NSS, PIN(E, 4), GPIO_OUT_HIGH) GPIO(USER_PRES_L, PIN(C, 5), GPIO_ODR_HIGH) |