diff options
author | Daisuke Nojiri <dnojiri@chromium.org> | 2021-03-25 03:33:44 +0000 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2021-03-25 03:41:10 +0000 |
commit | 9b1155c2d10b611050f99dbd8e993338ec8a47bb (patch) | |
tree | c98b746fb9e4ef2ffe2e8cd583f809d398b33dd9 | |
parent | 180a09484c9c6f94c3e2c8ec2ebd229b055efdb7 (diff) | |
download | chrome-ec-9b1155c2d10b611050f99dbd8e993338ec8a47bb.tar.gz |
Revert "Refactor CONFIG_FLASH_SIZE to CONFIG_FLASH_SIZE_BYTES"
This reverts commit 6f14eda97eae2fa3d98f6e87c46dc114169cedb1.
Reason for revert:
/opt/coreboot-sdk/lib/gcc/arm-eabi/8.3.0/../../../../arm-eabi/bin/ld:build/coachz/firmware_image.lds:3336: nonconstant expression for load base
Original change's description:
> Refactor CONFIG_FLASH_SIZE to CONFIG_FLASH_SIZE_BYTES
>
> In Zephyr CONFIG_FLASH_SIZE is a Kconfig value that is used
> throughout. The issue is that the units don't match. In
> Zephyr the value is in KiB instead of bytes. This refactor
> simply renames CONFIG_FLASH_SIZE in platform/ec to include
> the unit (via _BYTES).
>
> BRANCH=none
> BUG=b:174873770
> TEST=make buildall
> be generated by the build instead of per board
>
> Signed-off-by: Yuval Peress <peress@chromium.org>
> Change-Id: I44bf3c7a20fcf62aaa9ae15715be78db4210f384
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2627638
> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
> (cherry picked from commit 9e422c3c05fdd324565049b09be27c446f9dc0ca)
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2782078
> Reviewed-by: Wai-Hong Tam <waihong@google.com>
> Commit-Queue: Wai-Hong Tam <waihong@google.com>
> Tested-by: Wai-Hong Tam <waihong@google.com>
Bug: b:174873770
Change-Id: I83361fe984e495f5d585bae62f29bdfb23229900
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2785270
Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org>
98 files changed, 144 insertions, 150 deletions
diff --git a/baseboard/dedede/baseboard.h b/baseboard/dedede/baseboard.h index 11cc96b1ad..adedd00a42 100644 --- a/baseboard/dedede/baseboard.h +++ b/baseboard/dedede/baseboard.h @@ -28,7 +28,7 @@ #define NPCX_TACH_SEL2 0 /* No tach. */ /* Internal SPI flash on NPCX7 */ - #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) + #define CONFIG_FLASH_SIZE (512 * 1024) #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ #elif defined(VARIANT_DEDEDE_EC_IT8320) diff --git a/baseboard/grunt/baseboard.h b/baseboard/grunt/baseboard.h index ecb1063706..c5d3a5dde5 100644 --- a/baseboard/grunt/baseboard.h +++ b/baseboard/grunt/baseboard.h @@ -20,7 +20,7 @@ /* Internal SPI flash on NPCX7 */ /* Flash is 1MB but reserve half for future use. */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) +#define CONFIG_FLASH_SIZE (512 * 1024) #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ diff --git a/baseboard/hatch/baseboard.h b/baseboard/hatch/baseboard.h index 24cc045893..0655fdeab5 100644 --- a/baseboard/hatch/baseboard.h +++ b/baseboard/hatch/baseboard.h @@ -22,7 +22,7 @@ #define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ #define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ /* Internal SPI flash on NPCX796FC is 512 kB */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) +#define CONFIG_FLASH_SIZE (512 * 1024) #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ #define CONFIG_I2C diff --git a/baseboard/kalista/baseboard.h b/baseboard/kalista/baseboard.h index 97b91d886f..708a8ba990 100644 --- a/baseboard/kalista/baseboard.h +++ b/baseboard/kalista/baseboard.h @@ -28,7 +28,7 @@ #define CONFIG_KEYBOARD_PROTOCOL_MKBP #define CONFIG_MKBP_USE_HOST_EVENT #define CONFIG_DPTF -#define CONFIG_FLASH_SIZE_BYTES 0x80000 +#define CONFIG_FLASH_SIZE 0x80000 #define CONFIG_FPU #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER @@ -143,7 +143,7 @@ #define CONFIG_RW_B #define CONFIG_RW_B_MEM_OFF CONFIG_RO_MEM_OFF #undef CONFIG_RO_SIZE -#define CONFIG_RO_SIZE (CONFIG_FLASH_SIZE_BYTES / 4) +#define CONFIG_RO_SIZE (CONFIG_FLASH_SIZE / 4) #undef CONFIG_RW_SIZE #define CONFIG_RW_SIZE CONFIG_RO_SIZE #define CONFIG_RW_A_STORAGE_OFF CONFIG_RW_STORAGE_OFF diff --git a/baseboard/nucleo-f412zg/base-board.h b/baseboard/nucleo-f412zg/base-board.h index 31b4a73131..7b69fde7c5 100644 --- a/baseboard/nucleo-f412zg/base-board.h +++ b/baseboard/nucleo-f412zg/base-board.h @@ -62,7 +62,7 @@ #define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE) #define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - \ +#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE - \ (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF)) #define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF diff --git a/baseboard/nucleo-h743zi/base-board.h b/baseboard/nucleo-h743zi/base-board.h index 52744da323..0bf91efd83 100644 --- a/baseboard/nucleo-h743zi/base-board.h +++ b/baseboard/nucleo-h743zi/base-board.h @@ -54,13 +54,12 @@ * We need 2 independently erasable blocks, at a minimum. */ #define CONFIG_ROLLBACK_SIZE (2 * CONFIG_FLASH_BANK_SIZE) -#define CONFIG_ROLLBACK_OFF ((CONFIG_FLASH_SIZE_BYTES / 2) - \ - CONFIG_ROLLBACK_SIZE) +#define CONFIG_ROLLBACK_OFF ((CONFIG_FLASH_SIZE / 2) - CONFIG_ROLLBACK_SIZE) #define CONFIG_RO_MEM_OFF 0 #define CONFIG_RO_SIZE CONFIG_ROLLBACK_OFF -#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE_BYTES / 2) -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES / 2) +#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE / 2) +#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE / 2) #define CONFIG_RO_STORAGE_OFF 0 #define CONFIG_RW_STORAGE_OFF 0 diff --git a/baseboard/octopus/baseboard.h b/baseboard/octopus/baseboard.h index 82c025231c..a20b7bc8de 100644 --- a/baseboard/octopus/baseboard.h +++ b/baseboard/octopus/baseboard.h @@ -35,7 +35,7 @@ /* Internal SPI flash on NPCX7 */ /* Flash is 1MB but reserve half for future use. */ - #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) + #define CONFIG_FLASH_SIZE (512 * 1024) #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ diff --git a/baseboard/volteer/baseboard.h b/baseboard/volteer/baseboard.h index 82b24e4c81..8dc48f4c8c 100644 --- a/baseboard/volteer/baseboard.h +++ b/baseboard/volteer/baseboard.h @@ -19,7 +19,7 @@ #define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ #define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ /* Internal SPI flash on NPCX796FC is 512 kB */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) +#define CONFIG_FLASH_SIZE (512 * 1024) #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ diff --git a/baseboard/zork/baseboard.h b/baseboard/zork/baseboard.h index 652ac95046..a827a44474 100644 --- a/baseboard/zork/baseboard.h +++ b/baseboard/zork/baseboard.h @@ -19,7 +19,7 @@ #define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ /* Internal SPI flash on NPCX7 */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) +#define CONFIG_FLASH_SIZE (512 * 1024) #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q40 /* Internal SPI flash type. */ diff --git a/board/ambassador/board.h b/board/ambassador/board.h index 0237cf8719..ebaf8201ce 100644 --- a/board/ambassador/board.h +++ b/board/ambassador/board.h @@ -16,7 +16,7 @@ #define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ /* Internal SPI flash on NPCX796FC is 512 kB */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) +#define CONFIG_FLASH_SIZE (512 * 1024) #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ diff --git a/board/arcada_ish/board.h b/board/arcada_ish/board.h index 13c62c6195..3d4d9a044f 100644 --- a/board/arcada_ish/board.h +++ b/board/arcada_ish/board.h @@ -19,7 +19,7 @@ #undef CONFIG_DEBUG_ASSERT #define CONFIG_CLOCK_CRYSTAL /* EC */ -#define CONFIG_FLASH_SIZE_BYTES 0x80000 +#define CONFIG_FLASH_SIZE 0x80000 #define CONFIG_FPU #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER diff --git a/board/asurada_scp/board.h b/board/asurada_scp/board.h index 82e0602a53..debaedfac5 100644 --- a/board/asurada_scp/board.h +++ b/board/asurada_scp/board.h @@ -10,7 +10,7 @@ #define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD) | CC_MASK(CC_IPI))) -#define CONFIG_FLASH_SIZE_BYTES CONFIG_RAM_BASE +#define CONFIG_FLASH_SIZE CONFIG_RAM_BASE #define CONFIG_LTO #define CONFIG_UART_CONSOLE 0 diff --git a/board/atlas/board.h b/board/atlas/board.h index 0442225d30..8107f16b6b 100644 --- a/board/atlas/board.h +++ b/board/atlas/board.h @@ -34,7 +34,7 @@ #define CONFIG_SHA256_UNROLLED /* Internal SPI flash on NPCX7 */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* It's really 1MB. */ +#define CONFIG_FLASH_SIZE (512 * 1024) /* It's really 1MB. */ #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ diff --git a/board/atlas_ish/board.h b/board/atlas_ish/board.h index 5e75cbe7c0..fe5cdedc9d 100644 --- a/board/atlas_ish/board.h +++ b/board/atlas_ish/board.h @@ -25,7 +25,7 @@ #undef CONFIG_DEBUG_ASSERT #define CONFIG_CLOCK_CRYSTAL /* EC */ -#define CONFIG_FLASH_SIZE_BYTES 0x80000 +#define CONFIG_FLASH_SIZE 0x80000 #define CONFIG_FPU #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER diff --git a/board/cheza/board.h b/board/cheza/board.h index f9fd3bff62..e0aa3cd061 100644 --- a/board/cheza/board.h +++ b/board/cheza/board.h @@ -28,7 +28,7 @@ #define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ /* Internal SPI flash on NPCX7 */ -#define CONFIG_FLASH_SIZE_BYTES (1024 * 1024) /* 1MB internal spi flash */ +#define CONFIG_FLASH_SIZE (1024 * 1024) /* 1MB internal spi flash */ #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ #define CONFIG_HOSTCMD_FLASH_SPI_INFO diff --git a/board/chocodile_vpdmcu/board.h b/board/chocodile_vpdmcu/board.h index 3564a50753..09adee47b5 100644 --- a/board/chocodile_vpdmcu/board.h +++ b/board/chocodile_vpdmcu/board.h @@ -27,7 +27,7 @@ #define CONFIG_RO_SIZE 0 /* Fake full size if we had a RO partition */ #undef CONFIG_RW_SIZE -#define CONFIG_RW_SIZE CONFIG_FLASH_SIZE_BYTES +#define CONFIG_RW_SIZE CONFIG_FLASH_SIZE #endif /* HAS_TASK_CONSOLE */ /* 48 MHz SYSCLK clock frequency */ diff --git a/board/coachz/board.h b/board/coachz/board.h index 1eb0aa7601..255bacd670 100644 --- a/board/coachz/board.h +++ b/board/coachz/board.h @@ -30,7 +30,7 @@ #define CONFIG_BUTTON_TRIGGERED_RECOVERY /* Internal SPI flash on NPCX7 */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ +#define CONFIG_FLASH_SIZE (512 * 1024) /* 512KB internal spi flash */ /* Battery */ #define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" diff --git a/board/coral/board.h b/board/coral/board.h index c88ee4e701..3f09b7ebdd 100644 --- a/board/coral/board.h +++ b/board/coral/board.h @@ -165,7 +165,7 @@ #undef CONFIG_MOTION_SENSE_SUSPEND_DELAY_US #define CONFIG_MOTION_SENSE_SUSPEND_DELAY_US (MSEC * 60) -#define CONFIG_FLASH_SIZE_BYTES 524288 +#define CONFIG_FLASH_SIZE 524288 #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q40 /* FIXME: Should be GD25LQ40? */ diff --git a/board/dooly/board.h b/board/dooly/board.h index 4c97fc0027..25ca27f211 100644 --- a/board/dooly/board.h +++ b/board/dooly/board.h @@ -16,7 +16,7 @@ #define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ /* Internal SPI flash on NPCX796FC is 512 kB */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) +#define CONFIG_FLASH_SIZE (512 * 1024) #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ diff --git a/board/drallion_ish/board.h b/board/drallion_ish/board.h index 483af9be22..7bfd6b395a 100644 --- a/board/drallion_ish/board.h +++ b/board/drallion_ish/board.h @@ -19,7 +19,7 @@ #undef CONFIG_DEBUG_ASSERT #define CONFIG_CLOCK_CRYSTAL /* EC */ -#define CONFIG_FLASH_SIZE_BYTES 0x80000 +#define CONFIG_FLASH_SIZE 0x80000 #define CONFIG_FPU #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER diff --git a/board/endeavour/board.h b/board/endeavour/board.h index a3d871604f..7bf8415cb9 100644 --- a/board/endeavour/board.h +++ b/board/endeavour/board.h @@ -27,7 +27,7 @@ #define CONFIG_KEYBOARD_PROTOCOL_MKBP #define CONFIG_MKBP_USE_HOST_EVENT #define CONFIG_DPTF -#define CONFIG_FLASH_SIZE_BYTES 0x80000 +#define CONFIG_FLASH_SIZE 0x80000 #define CONFIG_FPU #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER diff --git a/board/eve/board.h b/board/eve/board.h index 322d9a23f7..ea09b9c8e3 100644 --- a/board/eve/board.h +++ b/board/eve/board.h @@ -24,7 +24,7 @@ #define CONFIG_DEVICE_EVENT #define CONFIG_DPTF #define CONFIG_DPTF_MULTI_PROFILE -#define CONFIG_FLASH_SIZE_BYTES 0x80000 +#define CONFIG_FLASH_SIZE 0x80000 #define CONFIG_FPU /* 7 day delay before hibernate */ #undef CONFIG_HIBERNATE_DELAY_SEC diff --git a/board/fizz/board.h b/board/fizz/board.h index e3d0120fe5..4aaf9090af 100644 --- a/board/fizz/board.h +++ b/board/fizz/board.h @@ -28,7 +28,7 @@ #define CONFIG_KEYBOARD_PROTOCOL_MKBP #define CONFIG_MKBP_USE_HOST_EVENT #define CONFIG_DPTF -#define CONFIG_FLASH_SIZE_BYTES 0x80000 +#define CONFIG_FLASH_SIZE 0x80000 #define CONFIG_FPU #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER @@ -158,7 +158,7 @@ #define CONFIG_RW_B #define CONFIG_RW_B_MEM_OFF CONFIG_RO_MEM_OFF #undef CONFIG_RO_SIZE -#define CONFIG_RO_SIZE (CONFIG_FLASH_SIZE_BYTES / 4) +#define CONFIG_RO_SIZE (CONFIG_FLASH_SIZE / 4) #undef CONFIG_RW_SIZE #define CONFIG_RW_SIZE CONFIG_RO_SIZE #define CONFIG_RW_A_STORAGE_OFF CONFIG_RW_STORAGE_OFF diff --git a/board/glkrvp/board.h b/board/glkrvp/board.h index 0ee352bfab..97253f26cf 100644 --- a/board/glkrvp/board.h +++ b/board/glkrvp/board.h @@ -99,7 +99,7 @@ #define CONFIG_LOW_POWER_IDLE -#define CONFIG_FLASH_SIZE_BYTES 524288 +#define CONFIG_FLASH_SIZE 524288 #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q40 diff --git a/board/hammer/board.h b/board/hammer/board.h index f862a82d9b..4d0194ada5 100644 --- a/board/hammer/board.h +++ b/board/hammer/board.h @@ -58,7 +58,7 @@ #define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE) #define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - \ +#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE - \ (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF)) #define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF diff --git a/board/hatch_fp/board.h b/board/hatch_fp/board.h index e83489ec8c..b6f27d2815 100644 --- a/board/hatch_fp/board.h +++ b/board/hatch_fp/board.h @@ -71,7 +71,7 @@ #define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE) #define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - \ +#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE - \ (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF)) #define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF diff --git a/board/homestar/board.h b/board/homestar/board.h index f1a2ffb49c..b68863531d 100644 --- a/board/homestar/board.h +++ b/board/homestar/board.h @@ -30,7 +30,7 @@ #define CONFIG_BUTTON_TRIGGERED_RECOVERY /* Internal SPI flash on NPCX7 */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ +#define CONFIG_FLASH_SIZE (512 * 1024) /* 512KB internal spi flash */ /* Battery */ #define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" diff --git a/board/kukui_scp/board.h b/board/kukui_scp/board.h index 040a7a0b9f..fcd9fb6399 100644 --- a/board/kukui_scp/board.h +++ b/board/kukui_scp/board.h @@ -10,7 +10,7 @@ #define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD) | CC_MASK(CC_IPI))) -#define CONFIG_FLASH_SIZE_BYTES 0x58000 /* Image file size: 256KB */ +#define CONFIG_FLASH_SIZE 0x58000 /* Image file size: 256KB */ #undef CONFIG_LID_SWITCH #undef CONFIG_FW_INCLUDE_RO #define CONFIG_MKBP_EVENT diff --git a/board/lazor/board.h b/board/lazor/board.h index af65f9e900..dcefbe5ccc 100644 --- a/board/lazor/board.h +++ b/board/lazor/board.h @@ -11,7 +11,7 @@ #include "baseboard.h" /* Internal SPI flash on NPCX7 */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ +#define CONFIG_FLASH_SIZE (512 * 1024) /* 512KB internal spi flash */ /* Switchcap */ #define CONFIG_LN9310 diff --git a/board/mchpevb1/board.h b/board/mchpevb1/board.h index f4789e5b81..af5553be92 100644 --- a/board/mchpevb1/board.h +++ b/board/mchpevb1/board.h @@ -270,10 +270,10 @@ * Configure for smaller flash is OK for testing except * for SPI flash lock bit. */ - #define CONFIG_FLASH_SIZE_BYTES 524288 + #define CONFIG_FLASH_SIZE 524288 #define CONFIG_SPI_FLASH_W25X40 /* - * #define CONFIG_FLASH_SIZE_BYTES 0x1000000 + * #define CONFIG_FLASH_SIZE 0x1000000 * #define CONFIG_SPI_FLASH_W25Q128 */ diff --git a/board/nami/board.h b/board/nami/board.h index fe1877dfb6..5343abf660 100644 --- a/board/nami/board.h +++ b/board/nami/board.h @@ -24,7 +24,7 @@ #define CONFIG_CROS_BOARD_INFO #define CONFIG_CASE_CLOSED_DEBUG_EXTERNAL #define CONFIG_DPTF -#define CONFIG_FLASH_SIZE_BYTES 0x80000 +#define CONFIG_FLASH_SIZE 0x80000 #define CONFIG_FPU #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER diff --git a/board/nautilus/board.h b/board/nautilus/board.h index e226556dea..f8b64cb4b3 100644 --- a/board/nautilus/board.h +++ b/board/nautilus/board.h @@ -23,7 +23,7 @@ #define CONFIG_DPTF #define CONFIG_DPTF_MOTION_LID_NO_GMR_SENSOR #define CONFIG_DPTF_MULTI_PROFILE -#define CONFIG_FLASH_SIZE_BYTES 0x80000 +#define CONFIG_FLASH_SIZE 0x80000 #define CONFIG_FPU #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER diff --git a/board/nocturne/board.h b/board/nocturne/board.h index 323d02dc83..5f481167dc 100644 --- a/board/nocturne/board.h +++ b/board/nocturne/board.h @@ -26,7 +26,7 @@ #define CONFIG_HIBERNATE_PSL /* Internal SPI flash on NPCX7 */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* It's really 1MB. */ +#define CONFIG_FLASH_SIZE (512 * 1024) /* It's really 1MB. */ #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ diff --git a/board/nocturne_fp/board.h b/board/nocturne_fp/board.h index ea19ab3325..3f4bda0b41 100644 --- a/board/nocturne_fp/board.h +++ b/board/nocturne_fp/board.h @@ -63,7 +63,7 @@ #define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE) #define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - \ +#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE - \ (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF)) #define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF diff --git a/board/npcx7_evb/board.h b/board/npcx7_evb/board.h index 2ce959cbbb..b93a11fcc5 100644 --- a/board/npcx7_evb/board.h +++ b/board/npcx7_evb/board.h @@ -69,10 +69,10 @@ #if defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M7FC) || \ defined(CHIP_VARIANT_NPCX7M7WC) #define CONFIG_SPI_FLASH_W25Q40 /* Internal spi flash type */ -#define CONFIG_FLASH_SIZE_BYTES 0x00080000 /* 512 KB internal spi flash */ +#define CONFIG_FLASH_SIZE 0x00080000 /* 512 KB internal spi flash */ #else #define CONFIG_SPI_FLASH_W25Q80 /* Internal spi flash type */ -#define CONFIG_FLASH_SIZE_BYTES 0x00100000 /* 1 MB internal spi flash */ +#define CONFIG_FLASH_SIZE 0x00100000 /* 1 MB internal spi flash */ #endif /* New features on npcx7 ec */ diff --git a/board/npcx_evb/board.h b/board/npcx_evb/board.h index b97bf43047..db7d2cc39e 100644 --- a/board/npcx_evb/board.h +++ b/board/npcx_evb/board.h @@ -19,7 +19,7 @@ #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */ #define CONFIG_SPI_FLASH_PORT 0 #define CONFIG_SPI_FLASH -#define CONFIG_FLASH_SIZE_BYTES 0x00800000 /* 8MB spi flash */ +#define CONFIG_FLASH_SIZE 0x00800000 /* 8MB spi flash */ #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q64 #define CONFIG_I2C diff --git a/board/npcx_evb_arm/board.h b/board/npcx_evb_arm/board.h index 582807a1b2..40f001f0a3 100644 --- a/board/npcx_evb_arm/board.h +++ b/board/npcx_evb_arm/board.h @@ -15,7 +15,7 @@ /* Optional features */ #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */ -#define CONFIG_FLASH_SIZE_BYTES 0x00800000 /* 8MB spi flash */ +#define CONFIG_FLASH_SIZE 0x00800000 /* 8MB spi flash */ #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q64 #define CONFIG_I2C diff --git a/board/pompom/board.h b/board/pompom/board.h index 81457fc5af..328aa12106 100644 --- a/board/pompom/board.h +++ b/board/pompom/board.h @@ -12,7 +12,7 @@ #include "board_revs.h" /* Internal SPI flash on NPCX7 */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ +#define CONFIG_FLASH_SIZE (512 * 1024) /* 512KB internal spi flash */ /* Keyboard */ #define CONFIG_KEYBOARD_BOARD_CONFIG diff --git a/board/poppy/board.h b/board/poppy/board.h index 6826851c71..72b3a618a4 100644 --- a/board/poppy/board.h +++ b/board/poppy/board.h @@ -26,7 +26,7 @@ #define CONFIG_DPTF_MULTI_PROFILE #endif #define CONFIG_EMULATED_SYSRQ -#define CONFIG_FLASH_SIZE_BYTES 0x80000 +#define CONFIG_FLASH_SIZE 0x80000 #define CONFIG_FPU #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER diff --git a/board/puff/board.h b/board/puff/board.h index c892bbff1c..078769622f 100644 --- a/board/puff/board.h +++ b/board/puff/board.h @@ -16,7 +16,7 @@ #define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ /* Internal SPI flash on NPCX796FC is 512 kB */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) +#define CONFIG_FLASH_SIZE (512 * 1024) #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ diff --git a/board/rammus/board.h b/board/rammus/board.h index 89ec43c255..81f76b842d 100644 --- a/board/rammus/board.h +++ b/board/rammus/board.h @@ -16,7 +16,7 @@ #define CONFIG_CRC8 #define CONFIG_CROS_BOARD_INFO #define CONFIG_DPTF -#define CONFIG_FLASH_SIZE_BYTES 0x80000 +#define CONFIG_FLASH_SIZE 0x80000 #define CONFIG_FPU #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER diff --git a/board/reef/board.h b/board/reef/board.h index a22bce3d70..39015541fe 100644 --- a/board/reef/board.h +++ b/board/reef/board.h @@ -162,7 +162,7 @@ #undef CONFIG_MOTION_SENSE_SUSPEND_DELAY_US #define CONFIG_MOTION_SENSE_SUSPEND_DELAY_US (MSEC * 60) -#define CONFIG_FLASH_SIZE_BYTES 524288 +#define CONFIG_FLASH_SIZE 524288 #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q40 /* FIXME: Should be GD25LQ40? */ diff --git a/board/reef_mchp/board.h b/board/reef_mchp/board.h index ef3356bb9d..cef9912be3 100644 --- a/board/reef_mchp/board.h +++ b/board/reef_mchp/board.h @@ -166,7 +166,7 @@ #define CONFIG_SPI_FLASH_PORT 0 #define CONFIG_SPI_FLASH -#define CONFIG_FLASH_SIZE_BYTES 524288 +#define CONFIG_FLASH_SIZE 524288 #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q40 /* FIXME: Should be GD25LQ40? */ diff --git a/board/servo_v4p1/board.h b/board/servo_v4p1/board.h index a21784e261..02bc4431ef 100644 --- a/board/servo_v4p1/board.h +++ b/board/servo_v4p1/board.h @@ -67,7 +67,7 @@ #define CONFIG_RW_MEM_OFF (CONFIG_FW_PSTATE_OFF + CONFIG_FW_PSTATE_SIZE) #define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - \ +#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE - \ (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF)) #define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF diff --git a/board/stm32l476g-eval/board.h b/board/stm32l476g-eval/board.h index 3124779fd7..7d7616822b 100644 --- a/board/stm32l476g-eval/board.h +++ b/board/stm32l476g-eval/board.h @@ -10,8 +10,8 @@ #ifdef CTS_MODULE /* CTS tests are small. We can use smaller size to expedite flash time. */ -#undef CONFIG_FLASH_SIZE_BYTES -#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256k */ +#undef CONFIG_FLASH_SIZE +#define CONFIG_FLASH_SIZE 0x00040000 /* 256k */ #endif /* Optional features */ diff --git a/board/tglrvp_ish/board.h b/board/tglrvp_ish/board.h index 7ab88641ea..2b7d86a140 100644 --- a/board/tglrvp_ish/board.h +++ b/board/tglrvp_ish/board.h @@ -26,7 +26,7 @@ #define CONFIG_CLOCK_CRYSTAL #define CONFIG_ISH_UART_0 /* EC */ -#define CONFIG_FLASH_SIZE_BYTES 0x80000 +#define CONFIG_FLASH_SIZE 0x80000 #define CONFIG_FPU #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER diff --git a/board/trogdor/board.h b/board/trogdor/board.h index 636b3dfead..aa9d49a3cd 100644 --- a/board/trogdor/board.h +++ b/board/trogdor/board.h @@ -22,7 +22,7 @@ #define CONFIG_I2C_DEBUG /* Internal SPI flash on NPCX7 */ -#define CONFIG_FLASH_SIZE_BYTES (1024 * 1024) /* 1MB internal spi flash */ +#define CONFIG_FLASH_SIZE (1024 * 1024) /* 1MB internal spi flash */ /* Keyboard */ #define CONFIG_KEYBOARD_BOARD_CONFIG diff --git a/board/volteer_ish/board.h b/board/volteer_ish/board.h index 6cc4057702..752ea283d5 100644 --- a/board/volteer_ish/board.h +++ b/board/volteer_ish/board.h @@ -26,7 +26,7 @@ #define CONFIG_CLOCK_CRYSTAL #define CONFIG_ISH_UART_0 /* EC */ -#define CONFIG_FLASH_SIZE_BYTES 0x80000 +#define CONFIG_FLASH_SIZE 0x80000 #define CONFIG_FPU #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER diff --git a/board/zinger/hardware.c b/board/zinger/hardware.c index 7e1f29da38..ceeac38d38 100644 --- a/board/zinger/hardware.c +++ b/board/zinger/hardware.c @@ -308,8 +308,7 @@ int flash_physical_write(int offset, int size, const char *data) int res = EC_SUCCESS; int i; - if ((uint32_t)address > - CONFIG_PROGRAM_MEMORY_BASE + CONFIG_FLASH_SIZE_BYTES) + if ((uint32_t)address > CONFIG_PROGRAM_MEMORY_BASE + CONFIG_FLASH_SIZE) return EC_ERROR_INVAL; /* unlock CR if needed */ diff --git a/chip/host/config_chip.h b/chip/host/config_chip.h index 84e254d8a0..195744c556 100644 --- a/chip/host/config_chip.h +++ b/chip/host/config_chip.h @@ -10,14 +10,14 @@ /* Memory mapping */ #if !defined(TEST_NVMEM) && !defined(TEST_CR50_FUZZ) -#define CONFIG_FLASH_SIZE_BYTES 0x00020000 +#define CONFIG_FLASH_SIZE 0x00020000 #define CONFIG_FLASH_BANK_SIZE 0x1000 #else -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) +#define CONFIG_FLASH_SIZE (512 * 1024) #define CONFIG_FLASH_BANK_SIZE 0x800 #endif -extern char __host_flash[CONFIG_FLASH_SIZE_BYTES]; +extern char __host_flash[CONFIG_FLASH_SIZE]; #define CONFIG_PROGRAM_MEMORY_BASE ((uintptr_t)__host_flash) #define CONFIG_FLASH_ERASE_SIZE 0x0010 /* erase bank size */ diff --git a/chip/host/flash.c b/chip/host/flash.c index 486c418065..9f79298d60 100644 --- a/chip/host/flash.c +++ b/chip/host/flash.c @@ -14,7 +14,7 @@ #include "util.h" /* This needs to be aligned to the erase bank size for NVCTR. */ -__aligned(CONFIG_FLASH_ERASE_SIZE) char __host_flash[CONFIG_FLASH_SIZE_BYTES]; +__aligned(CONFIG_FLASH_ERASE_SIZE) char __host_flash[CONFIG_FLASH_SIZE]; uint8_t __host_flash_protect[PHYSICAL_BANKS]; /* Override this function to make flash erase/write operation fail */ diff --git a/chip/ish/config_flash_layout.h b/chip/ish/config_flash_layout.h index 9a6cc4f28b..0430baf3eb 100644 --- a/chip/ish/config_flash_layout.h +++ b/chip/ish/config_flash_layout.h @@ -26,9 +26,9 @@ #define CONFIG_MAPPED_STORAGE_BASE 0x0 -#define CONFIG_EC_PROTECTED_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x20000) +#define CONFIG_EC_PROTECTED_STORAGE_OFF (CONFIG_FLASH_SIZE - 0x20000) #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000 -#define CONFIG_EC_WRITABLE_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x40000) +#define CONFIG_EC_WRITABLE_STORAGE_OFF (CONFIG_FLASH_SIZE - 0x40000) #define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000 /* Unused for ISH - loader is external to ISH FW */ diff --git a/chip/it83xx/config_chip_it8320.h b/chip/it83xx/config_chip_it8320.h index 2918698e64..6163ef8fb9 100644 --- a/chip/it83xx/config_chip_it8320.h +++ b/chip/it83xx/config_chip_it8320.h @@ -36,7 +36,7 @@ * doesn't support a write-protect pin, and if we make the write-protection * permanent, it can't be undone easily enough to support RMA. */ -#define CONFIG_FLASH_SIZE_BYTES 0x00040000 +#define CONFIG_FLASH_SIZE 0x00040000 /* For IT8320BX, we have to reload cc parameters after ec softreset. */ #define IT83XX_USBPD_CC_PARAMETER_RELOAD /* @@ -53,7 +53,7 @@ */ #define IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES #elif defined(CHIP_VARIANT_IT8320DX) -#define CONFIG_FLASH_SIZE_BYTES 0x00080000 +#define CONFIG_FLASH_SIZE 0x00080000 #define CONFIG_IT83XX_FLASH_CLOCK_48MHZ /* * Disable eSPI pad, then PLL change diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h index 0a66e14fee..a3113907fd 100644 --- a/chip/it83xx/config_chip_it8xxx2.h +++ b/chip/it83xx/config_chip_it8xxx2.h @@ -37,7 +37,7 @@ #if defined(CHIP_VARIANT_IT83202BX) /* TODO(b/133460224): enable properly chip config option. */ -#define CONFIG_FLASH_SIZE_BYTES 0x00080000 +#define CONFIG_FLASH_SIZE 0x00080000 #define CONFIG_RAM_BASE 0x80080000 #define CONFIG_RAM_SIZE 0x00010000 @@ -80,7 +80,7 @@ || defined(CHIP_VARIANT_IT81202AX_1024) \ || defined(CHIP_VARIANT_IT81302BX_1024) \ || defined(CHIP_VARIANT_IT81202BX_1024) -#define CONFIG_FLASH_SIZE_BYTES 0x00100000 +#define CONFIG_FLASH_SIZE 0x00100000 #define CONFIG_RAM_BASE 0x80100000 #define CONFIG_RAM_SIZE 0x0000f000 diff --git a/chip/it83xx/flash.c b/chip/it83xx/flash.c index 67b51713a6..df55ad77f4 100644 --- a/chip/it83xx/flash.c +++ b/chip/it83xx/flash.c @@ -370,7 +370,7 @@ static enum flash_wp_status flash_check_wp(void) enum flash_wp_status wp_status; int all_bank_count, bank; - all_bank_count = CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE; + all_bank_count = CONFIG_FLASH_SIZE / CONFIG_FLASH_BANK_SIZE; for (bank = 0; bank < all_bank_count; bank++) { if (!(IT83XX_GCTRL_EWPR0PFEC(FWP_REG(bank)) & FWP_MASK(bank))) @@ -547,7 +547,7 @@ int flash_physical_protect_now(int all) if (all) { /* Protect the entire flash */ flash_protect_banks(0, - CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE, + CONFIG_FLASH_SIZE / CONFIG_FLASH_BANK_SIZE, FLASH_WP_EC); all_protected = 1; } else { @@ -712,11 +712,11 @@ int flash_pre_init(void) if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) { /* Protect the entire flash of host interface */ flash_protect_banks(0, - CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE, + CONFIG_FLASH_SIZE / CONFIG_FLASH_BANK_SIZE, FLASH_WP_HOST); /* Protect the entire flash of DBGR interface */ flash_protect_banks(0, - CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE, + CONFIG_FLASH_SIZE / CONFIG_FLASH_BANK_SIZE, FLASH_WP_DBGR); /* * Write protect is asserted. If we want RO flash protected, diff --git a/chip/lm4/config_chip.h b/chip/lm4/config_chip.h index 4e442004c9..8abe059e5b 100644 --- a/chip/lm4/config_chip.h +++ b/chip/lm4/config_chip.h @@ -61,7 +61,7 @@ * in order to emulate per-bank write-protection UNTIL REBOOT. The hardware * doesn't support a write-protect pin, and if we make the write-protection * permanent, it can't be undone easily enough to support RMA. */ -#define CONFIG_FLASH_SIZE_BYTES 0x00040000 +#define CONFIG_FLASH_SIZE 0x00040000 /****************************************************************************/ /* Define our flash layout. */ diff --git a/chip/lm4/flash.c b/chip/lm4/flash.c index 5e0c6510f3..4f7e905e21 100644 --- a/chip/lm4/flash.c +++ b/chip/lm4/flash.c @@ -193,7 +193,7 @@ int flash_physical_protect_now(int all) if (all) { /* Protect the entire flash */ all_protected = 1; - protect_banks(0, CONFIG_FLASH_SIZE_BYTES / + protect_banks(0, CONFIG_FLASH_SIZE / CONFIG_FLASH_BANK_SIZE); } else /* Protect the WP region (read-only section and pstate) */ diff --git a/chip/max32660/config_chip.h b/chip/max32660/config_chip.h index c97c246bb7..b74ec591ad 100644 --- a/chip/max32660/config_chip.h +++ b/chip/max32660/config_chip.h @@ -61,7 +61,7 @@ * in order to emulate per-bank write-protection UNTIL REBOOT. The hardware * doesn't support a write-protect pin, and if we make the write-protection * permanent, it can't be undone easily enough to support RMA. */ -#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256K MAX32660 FLASH Size */ +#define CONFIG_FLASH_SIZE 0x00040000 /* 256K MAX32660 FLASH Size */ /****************************************************************************/ /* Define our flash layout. */ diff --git a/chip/mchp/lfw/ec_lfw.c b/chip/mchp/lfw/ec_lfw.c index 5f8d5da806..edd945037c 100644 --- a/chip/mchp/lfw/ec_lfw.c +++ b/chip/mchp/lfw/ec_lfw.c @@ -141,7 +141,7 @@ static int spi_flash_readloc(uint8_t *buf_usr, (offset >> 8) & 0xFF, offset & 0xFF}; - if (offset + bytes > CONFIG_FLASH_SIZE_BYTES) + if (offset + bytes > CONFIG_FLASH_SIZE) return EC_ERROR_INVAL; __hw_clock_source_set(0); /* restart free run timer */ diff --git a/chip/mec1322/config_flash_layout.h b/chip/mec1322/config_flash_layout.h index a5b064b8cc..3ab249668d 100644 --- a/chip/mec1322/config_flash_layout.h +++ b/chip/mec1322/config_flash_layout.h @@ -21,9 +21,9 @@ #define CONFIG_SPI_FLASH /* EC region of SPI resides at end of ROM, protected region follows writable */ -#define CONFIG_EC_PROTECTED_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x20000) +#define CONFIG_EC_PROTECTED_STORAGE_OFF (CONFIG_FLASH_SIZE - 0x20000) #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000 -#define CONFIG_EC_WRITABLE_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x40000) +#define CONFIG_EC_WRITABLE_STORAGE_OFF (CONFIG_FLASH_SIZE - 0x40000) #define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000 /* Loader resides at the beginning of program memory */ diff --git a/chip/mec1322/lfw/ec_lfw.c b/chip/mec1322/lfw/ec_lfw.c index 8875b6ca02..39f4e378ae 100644 --- a/chip/mec1322/lfw/ec_lfw.c +++ b/chip/mec1322/lfw/ec_lfw.c @@ -83,7 +83,7 @@ static int spi_flash_readloc(uint8_t *buf_usr, (offset >> 8) & 0xFF, offset & 0xFF}; - if (offset + bytes > CONFIG_FLASH_SIZE_BYTES) + if (offset + bytes > CONFIG_FLASH_SIZE) return EC_ERROR_INVAL; return spi_transaction(SPI_FLASH_DEVICE, cmd, 4, buf_usr, bytes); diff --git a/chip/npcx/config_chip-npcx9.h b/chip/npcx/config_chip-npcx9.h index 8f3a0ebc32..9f7b0f52d0 100644 --- a/chip/npcx/config_chip-npcx9.h +++ b/chip/npcx/config_chip-npcx9.h @@ -102,7 +102,7 @@ #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q40 /* Internal spi flash type */ -#define CONFIG_FLASH_SIZE_BYTES 0x00080000 /* 512 KB internal spi flash */ +#define CONFIG_FLASH_SIZE 0x00080000 /* 512 KB internal spi flash */ #endif /* __CROS_EC_CONFIG_CHIP_NPCX9_H */ diff --git a/chip/npcx/flash.c b/chip/npcx/flash.c index a5f656f8ca..7afb413c2c 100644 --- a/chip/npcx/flash.c +++ b/chip/npcx/flash.c @@ -329,7 +329,7 @@ static int flash_set_status_for_prot(int reg1, int reg2) static int flash_check_prot_range(unsigned int offset, unsigned int bytes) { /* Invalid value */ - if (offset + bytes > CONFIG_FLASH_SIZE_BYTES) + if (offset + bytes > CONFIG_FLASH_SIZE) return EC_ERROR_INVAL; /* Check if ranges overlap */ if (MAX(addr_prot_start, offset) < MIN(addr_prot_start + @@ -362,7 +362,7 @@ static int flash_check_prot_reg(unsigned int offset, unsigned int bytes) sr2 = flash_get_status2(); /* Invalid value */ - if (offset + bytes > CONFIG_FLASH_SIZE_BYTES) + if (offset + bytes > CONFIG_FLASH_SIZE) return EC_ERROR_INVAL; /* Compute current protect range */ @@ -386,7 +386,7 @@ static int flash_write_prot_reg(unsigned int offset, unsigned int bytes, uint8_t sr2 = flash_get_status2(); /* Invalid values */ - if (offset + bytes > CONFIG_FLASH_SIZE_BYTES) + if (offset + bytes > CONFIG_FLASH_SIZE) return EC_ERROR_INVAL; /* Compute desired protect range */ diff --git a/chip/nrf51/config_chip.h b/chip/nrf51/config_chip.h index f63fff0fe3..7295ab9360 100644 --- a/chip/nrf51/config_chip.h +++ b/chip/nrf51/config_chip.h @@ -37,7 +37,7 @@ /* Flash mapping */ #define CONFIG_PROGRAM_MEMORY_BASE 0x00000000 -#define CONFIG_FLASH_SIZE_BYTES 0x00040000 +#define CONFIG_FLASH_SIZE 0x00040000 #define CONFIG_FLASH_BANK_SIZE 0x1000 /* Memory-mapped internal flash */ diff --git a/chip/stm32/config-stm32f03x.h b/chip/stm32/config-stm32f03x.h index 3c51086c26..84266cdbfc 100644 --- a/chip/stm32/config-stm32f03x.h +++ b/chip/stm32/config-stm32f03x.h @@ -4,10 +4,10 @@ */ #ifdef CHIP_VARIANT_STM32F03X8 -#define CONFIG_FLASH_SIZE_BYTES 0x00010000 +#define CONFIG_FLASH_SIZE 0x00010000 #define CONFIG_RAM_SIZE 0x00002000 #else -#define CONFIG_FLASH_SIZE_BYTES 0x00008000 +#define CONFIG_FLASH_SIZE 0x00008000 #define CONFIG_RAM_SIZE 0x00001000 #endif diff --git a/chip/stm32/config-stm32f05x.h b/chip/stm32/config-stm32f05x.h index 00bf45fde5..cab7b62d50 100644 --- a/chip/stm32/config-stm32f05x.h +++ b/chip/stm32/config-stm32f05x.h @@ -4,7 +4,7 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES (64 * 1024) +#define CONFIG_FLASH_SIZE (64 * 1024) #define CONFIG_FLASH_BANK_SIZE 0x1000 #define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */ #define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ diff --git a/chip/stm32/config-stm32f07x.h b/chip/stm32/config-stm32f07x.h index 918a117a22..199aef3361 100644 --- a/chip/stm32/config-stm32f07x.h +++ b/chip/stm32/config-stm32f07x.h @@ -4,7 +4,7 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES (128 * 1024) +#define CONFIG_FLASH_SIZE (128 * 1024) #define CONFIG_FLASH_BANK_SIZE 0x1000 #define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ #define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ diff --git a/chip/stm32/config-stm32f09x.h b/chip/stm32/config-stm32f09x.h index 9dc27a1fb2..3da8a342f2 100644 --- a/chip/stm32/config-stm32f09x.h +++ b/chip/stm32/config-stm32f09x.h @@ -8,7 +8,7 @@ * Flash physical size: 256KB * Write protect sectors: 31 4KB sectors, one 132KB sector */ -#define CONFIG_FLASH_SIZE_BYTES 0x00040000 +#define CONFIG_FLASH_SIZE 0x00040000 #define CONFIG_FLASH_BANK_SIZE 0x1000 #define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ #define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ @@ -62,7 +62,7 @@ #define CONFIG_EC_PROTECTED_STORAGE_OFF 0 #define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF #define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE (CONFIG_FLASH_SIZE_BYTES - \ +#define CONFIG_EC_WRITABLE_STORAGE_SIZE (CONFIG_FLASH_SIZE - \ CONFIG_EC_WRITABLE_STORAGE_OFF) #define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF diff --git a/chip/stm32/config-stm32f373.h b/chip/stm32/config-stm32f373.h index 3df5bfce67..b77b1d98a6 100644 --- a/chip/stm32/config-stm32f373.h +++ b/chip/stm32/config-stm32f373.h @@ -4,7 +4,7 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES 0x00040000 +#define CONFIG_FLASH_SIZE 0x00040000 #define CONFIG_FLASH_BANK_SIZE 0x2000 #define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ #define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ diff --git a/chip/stm32/config-stm32f4.h b/chip/stm32/config-stm32f4.h index 60b1affd3c..c64cc3089a 100644 --- a/chip/stm32/config-stm32f4.h +++ b/chip/stm32/config-stm32f4.h @@ -5,9 +5,9 @@ /* Memory mapping */ #ifdef CHIP_VARIANT_STM32F412 -# define CONFIG_FLASH_SIZE_BYTES (1 * 1024 * 1024) +# define CONFIG_FLASH_SIZE (1 * 1024 * 1024) #else -# define CONFIG_FLASH_SIZE_BYTES (512 * 1024) +# define CONFIG_FLASH_SIZE (512 * 1024) #endif /* 3 regions type: 16K, 64K and 128K */ @@ -16,7 +16,7 @@ #define SIZE_128KB (128 * 1024) #define CONFIG_FLASH_REGION_TYPE_COUNT 3 #define CONFIG_FLASH_MULTIPLE_REGION \ - (5 + (CONFIG_FLASH_SIZE_BYTES - SIZE_128KB) / SIZE_128KB) + (5 + (CONFIG_FLASH_SIZE - SIZE_128KB) / SIZE_128KB) /* Erasing 128K can take up to 2s, need to defer erase. */ #define CONFIG_FLASH_DEFERRED_ERASE @@ -50,7 +50,7 @@ #define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF #define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF #define CONFIG_EC_WRITABLE_STORAGE_SIZE \ - (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) + (CONFIG_FLASH_SIZE - CONFIG_EC_WRITABLE_STORAGE_OFF) #define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF #define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE diff --git a/chip/stm32/config-stm32f76x.h b/chip/stm32/config-stm32f76x.h index d027ad62fb..665bec36bf 100644 --- a/chip/stm32/config-stm32f76x.h +++ b/chip/stm32/config-stm32f76x.h @@ -4,7 +4,7 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES (2048 * 1024) +#define CONFIG_FLASH_SIZE (2048 * 1024) /* 3 regions type: 32K, 128K and 256K */ #define SIZE_32KB (32 * 1024) @@ -12,7 +12,7 @@ #define SIZE_256KB (256 * 1024) #define CONFIG_FLASH_REGION_TYPE_COUNT 3 #define CONFIG_FLASH_MULTIPLE_REGION \ - (5 + (CONFIG_FLASH_SIZE_BYTES - SIZE_256KB) / SIZE_256KB) + (5 + (CONFIG_FLASH_SIZE - SIZE_256KB) / SIZE_256KB) /* Erasing 256K can take up to 2s, need to defer erase. */ #define CONFIG_FLASH_DEFERRED_ERASE @@ -44,7 +44,7 @@ #define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF #define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF #define CONFIG_EC_WRITABLE_STORAGE_SIZE \ - (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) + (CONFIG_FLASH_SIZE - CONFIG_EC_WRITABLE_STORAGE_OFF) #define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF #define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE diff --git a/chip/stm32/config-stm32g41xb.h b/chip/stm32/config-stm32g41xb.h index da42faf2c3..ab8642b9e6 100644 --- a/chip/stm32/config-stm32g41xb.h +++ b/chip/stm32/config-stm32g41xb.h @@ -21,7 +21,7 @@ * without being constrained by flash space issue. Currently only using RO image * flashed with STM32 debugger. */ -#define CONFIG_FLASH_SIZE_BYTES (256 * 1024) +#define CONFIG_FLASH_SIZE (256 * 1024) #define CONFIG_FLASH_WRITE_SIZE 0x0004 #define CONFIG_FLASH_BANK_SIZE (2 * 1024) #define CONFIG_FLASH_ERASE_SIZE CONFIG_FLASH_BANK_SIZE diff --git a/chip/stm32/config-stm32h7x3.h b/chip/stm32/config-stm32h7x3.h index da94b09069..399e6a6f1a 100644 --- a/chip/stm32/config-stm32h7x3.h +++ b/chip/stm32/config-stm32h7x3.h @@ -4,7 +4,7 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES (2048 * 1024) +#define CONFIG_FLASH_SIZE (2048 * 1024) #define CONFIG_FLASH_ERASE_SIZE (128 * 1024) /* erase bank size */ /* always use 256-bit writes due to ECC */ #define CONFIG_FLASH_WRITE_SIZE 32 /* minimum write size */ @@ -32,7 +32,7 @@ #define CONFIG_RO_MEM_OFF 0 #define CONFIG_RO_SIZE (128 * 1024) -#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE_BYTES / 2) +#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE / 2) #define CONFIG_RW_SIZE (512 * 1024) #define CONFIG_RO_STORAGE_OFF 0 @@ -42,7 +42,7 @@ #define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF #define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF #define CONFIG_EC_WRITABLE_STORAGE_SIZE \ - (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) + (CONFIG_FLASH_SIZE - CONFIG_EC_WRITABLE_STORAGE_OFF) #define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF #define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE diff --git a/chip/stm32/config-stm32l100.h b/chip/stm32/config-stm32l100.h index 2c4efcc6df..579e31cb5b 100644 --- a/chip/stm32/config-stm32l100.h +++ b/chip/stm32/config-stm32l100.h @@ -4,7 +4,7 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES 0x00020000 +#define CONFIG_FLASH_SIZE 0x00020000 #define CONFIG_FLASH_BANK_SIZE 0x1000 #define CONFIG_FLASH_ERASE_SIZE 0x0100 /* erase bank size */ diff --git a/chip/stm32/config-stm32l15x.h b/chip/stm32/config-stm32l15x.h index 0b32f95572..afdc241e96 100644 --- a/chip/stm32/config-stm32l15x.h +++ b/chip/stm32/config-stm32l15x.h @@ -4,7 +4,7 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES 0x00020000 +#define CONFIG_FLASH_SIZE 0x00020000 #define CONFIG_FLASH_BANK_SIZE 0x1000 #define CONFIG_FLASH_ERASE_SIZE 0x0100 /* erase bank size */ diff --git a/chip/stm32/config-stm32l442.h b/chip/stm32/config-stm32l442.h index 54ba9bac8d..e9f3e04c53 100644 --- a/chip/stm32/config-stm32l442.h +++ b/chip/stm32/config-stm32l442.h @@ -4,7 +4,7 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256 kB */ +#define CONFIG_FLASH_SIZE 0x00040000 /* 256 kB */ #define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */ #define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ #define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */ diff --git a/chip/stm32/config-stm32l476.h b/chip/stm32/config-stm32l476.h index 2e0084fd94..9f6b35b8b1 100644 --- a/chip/stm32/config-stm32l476.h +++ b/chip/stm32/config-stm32l476.h @@ -4,7 +4,7 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES 0x00100000 /* 1 MB */ +#define CONFIG_FLASH_SIZE 0x00100000 /* 1 MB */ #define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */ #define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ #define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits (without 8 bits ECC) */ diff --git a/chip/stm32/flash-stm32f0.c b/chip/stm32/flash-stm32f0.c index a0aef5fe3f..e2ff2c779c 100644 --- a/chip/stm32/flash-stm32f0.c +++ b/chip/stm32/flash-stm32f0.c @@ -26,7 +26,7 @@ uint32_t flash_physical_get_protect_flags(void) { uint32_t flags = 0; uint32_t wrp01 = REG32(STM32_OPTB_BASE + STM32_OPTB_WRP01); -#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024 +#if CONFIG_FLASH_SIZE > 64 * 1024 uint32_t wrp23 = REG32(STM32_OPTB_BASE + STM32_OPTB_WRP23); #endif @@ -76,12 +76,12 @@ uint32_t flash_physical_get_protect_flags(void) switch (i) { case 8: -#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024 +#if CONFIG_FLASH_SIZE > 64 * 1024 case 24: #endif shift += 8; break; -#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024 +#if CONFIG_FLASH_SIZE > 64 * 1024 case 16: reg = 1; shift = 0; @@ -96,7 +96,7 @@ uint32_t flash_physical_get_protect_flags(void) for (i = 0; i < FLASH_REGION_COUNT; i++) { if (!(wrp01 & wrp_mask[i][0]) && (wrp01 & wrp_mask[i][0] << 8) == (wrp_mask[i][0] << 8)) -#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024 +#if CONFIG_FLASH_SIZE > 64 * 1024 if (!(wrp23 & wrp_mask[i][1]) && (wrp23 & wrp_mask[i][1] << 8) == (wrp_mask[i][1] << 8)) @@ -106,7 +106,7 @@ uint32_t flash_physical_get_protect_flags(void) #endif /* CONFIG_FLASH_PROTECT_RW || CONFIG_ROLLBACK */ if (wrp01 == 0xff00ff00) -#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024 +#if CONFIG_FLASH_SIZE > 64 * 1024 if (wrp23 == 0xff00ff00) #endif flags |= EC_FLASH_PROTECT_ALL_AT_BOOT; diff --git a/chip/stm32/flash-stm32f3.c b/chip/stm32/flash-stm32f3.c index bae4315b67..ea5ba1a1b6 100644 --- a/chip/stm32/flash-stm32f3.c +++ b/chip/stm32/flash-stm32f3.c @@ -36,7 +36,7 @@ struct ec_flash_bank const flash_bank_array[] = { .protect_size_exp = __fls(SIZE_128KB), }, { - .count = (CONFIG_FLASH_SIZE_BYTES - SIZE_256KB) / SIZE_256KB, + .count = (CONFIG_FLASH_SIZE - SIZE_256KB) / SIZE_256KB, .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), .size_exp = __fls(SIZE_256KB), .erase_size_exp = __fls(SIZE_256KB), @@ -70,7 +70,7 @@ struct ec_flash_bank const flash_bank_array[] = { .protect_size_exp = __fls(SIZE_64KB), }, { - .count = (CONFIG_FLASH_SIZE_BYTES - SIZE_128KB) / SIZE_128KB, + .count = (CONFIG_FLASH_SIZE - SIZE_128KB) / SIZE_128KB, .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), .size_exp = __fls(SIZE_128KB), .erase_size_exp = __fls(SIZE_128KB), diff --git a/chip/stm32/flash-stm32g4-l4.c b/chip/stm32/flash-stm32g4-l4.c index 360d63a739..27092a1156 100644 --- a/chip/stm32/flash-stm32g4-l4.c +++ b/chip/stm32/flash-stm32g4-l4.c @@ -46,7 +46,7 @@ * CONFIG_WP_STORAGE_SIZE -> size of RO region in bytes */ #define FLASH_PAGE_SIZE CONFIG_FLASH_BANK_SIZE -#define FLASH_PAGE_MAX_COUNT (CONFIG_FLASH_SIZE_BYTES / FLASH_PAGE_SIZE) +#define FLASH_PAGE_MAX_COUNT (CONFIG_FLASH_SIZE / FLASH_PAGE_SIZE) #define FLASH_RO_FIRST_PAGE_IDX WP_BANK_OFFSET #define FLASH_RO_LAST_PAGE_IDX ((CONFIG_WP_STORAGE_SIZE / FLASH_PAGE_SIZE) \ + FLASH_RO_FIRST_PAGE_IDX - 1) diff --git a/chip/stm32/flash-stm32h7.c b/chip/stm32/flash-stm32h7.c index 2797720b8f..a541b962d2 100644 --- a/chip/stm32/flash-stm32h7.c +++ b/chip/stm32/flash-stm32h7.c @@ -44,7 +44,7 @@ * not what is called 'bank' in the common code (ie Write-Protect sectors) * both have the same number of 128KB blocks. */ -#define HWBANK_SIZE (CONFIG_FLASH_SIZE_BYTES / 2) +#define HWBANK_SIZE (CONFIG_FLASH_SIZE / 2) #define BLOCKS_PER_HWBANK (HWBANK_SIZE / CONFIG_FLASH_ERASE_SIZE) #define BLOCKS_HWBANK_MASK (BIT(BLOCKS_PER_HWBANK) - 1) diff --git a/common/firmware_image.lds.S b/common/firmware_image.lds.S index 32e9758c22..fc1b1f1d7d 100644 --- a/common/firmware_image.lds.S +++ b/common/firmware_image.lds.S @@ -43,7 +43,7 @@ OUTPUT_ARCH(BFD_ARCH) MEMORY { FLASH (rx) : ORIGIN = CONFIG_PROGRAM_MEMORY_BASE, - LENGTH = CONFIG_FLASH_SIZE_BYTES + LENGTH = CONFIG_FLASH_SIZE #ifdef CONFIG_IPI IPI_BUFFER (rw) : ORIGIN = CONFIG_IPC_SHARED_OBJ_ADDR, LENGTH = (CONFIG_IPC_SHARED_OBJ_BUF_SIZE + 8) * 2 diff --git a/common/flash.c b/common/flash.c index ab3cd23df0..235121f51e 100644 --- a/common/flash.c +++ b/common/flash.c @@ -218,9 +218,9 @@ int flash_bank_start_offset(int bank) static int flash_range_ok(int offset, int size_req, int align) { if (offset < 0 || size_req < 0 || - offset > CONFIG_FLASH_SIZE_BYTES || - size_req > CONFIG_FLASH_SIZE_BYTES || - offset + size_req > CONFIG_FLASH_SIZE_BYTES || + offset > CONFIG_FLASH_SIZE || + size_req > CONFIG_FLASH_SIZE || + offset + size_req > CONFIG_FLASH_SIZE || (offset | size_req) & (align - 1)) return 0; /* Invalid range */ @@ -251,7 +251,7 @@ int flash_dataptr(int offset, int size_req, int align, const char **ptrp) if (ptrp) *ptrp = flash_physical_dataptr(offset); - return CONFIG_FLASH_SIZE_BYTES - offset; + return CONFIG_FLASH_SIZE - offset; } #endif @@ -979,7 +979,7 @@ static int command_flash_info(int argc, char **argv) { int i, flags; - ccprintf("Usable: %4d KB\n", CONFIG_FLASH_SIZE_BYTES / 1024); + ccprintf("Usable: %4d KB\n", CONFIG_FLASH_SIZE / 1024); ccprintf("Write: %4d B (ideal %d B)\n", CONFIG_FLASH_WRITE_SIZE, CONFIG_FLASH_WRITE_IDEAL_SIZE); #ifdef CONFIG_FLASH_MULTIPLE_REGION @@ -1234,7 +1234,7 @@ static enum ec_status flash_command_get_info(struct host_cmd_handler_args *args) #error "Flash: Bank size expected bigger or equal to erase size." #endif struct ec_flash_bank single_bank = { - .count = CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE, + .count = CONFIG_FLASH_SIZE / CONFIG_FLASH_BANK_SIZE, .size_exp = __fls(CONFIG_FLASH_BANK_SIZE), .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), .erase_size_exp = __fls(CONFIG_FLASH_ERASE_SIZE), @@ -1265,8 +1265,7 @@ static enum ec_status flash_command_get_info(struct host_cmd_handler_args *args) if (args->version >= 2) { args->response_size = sizeof(struct ec_response_flash_info_2); - r_2->flash_size = - CONFIG_FLASH_SIZE_BYTES - EC_FLASH_REGION_START; + r_2->flash_size = CONFIG_FLASH_SIZE - EC_FLASH_REGION_START; #if (CONFIG_FLASH_ERASED_VALUE32 == 0) r_2->flags = EC_FLASH_INFO_ERASE_TO_0; #else @@ -1286,7 +1285,7 @@ static enum ec_status flash_command_get_info(struct host_cmd_handler_args *args) #ifdef CONFIG_FLASH_MULTIPLE_REGION return EC_RES_INVALID_PARAM; #else - r_1->flash_size = CONFIG_FLASH_SIZE_BYTES - EC_FLASH_REGION_START; + r_1->flash_size = CONFIG_FLASH_SIZE - EC_FLASH_REGION_START; r_1->flags = 0; r_1->write_block_size = CONFIG_FLASH_WRITE_SIZE; r_1->erase_block_size = CONFIG_FLASH_ERASE_SIZE; diff --git a/common/fmap.c b/common/fmap.c index ecaa854ee9..001f83a184 100644 --- a/common/fmap.c +++ b/common/fmap.c @@ -101,7 +101,7 @@ const struct _ec_fmap { .fmap_ver_major = FMAP_VER_MAJOR, .fmap_ver_minor = FMAP_VER_MINOR, .fmap_base = CONFIG_PROGRAM_MEMORY_BASE, - .fmap_size = CONFIG_FLASH_SIZE_BYTES, + .fmap_size = CONFIG_FLASH_SIZE, /* Used to distinguish the EC FMAP from other FMAPs */ .fmap_name = "EC_FMAP", .fmap_nareas = NUM_EC_FMAP_AREAS, diff --git a/common/spi_flash.c b/common/spi_flash.c index c4346ef48b..3f003052bf 100644 --- a/common/spi_flash.c +++ b/common/spi_flash.c @@ -153,7 +153,7 @@ int spi_flash_read(uint8_t *buf_usr, unsigned int offset, unsigned int bytes) { int i, read_size, ret, spi_addr; uint8_t cmd[4]; - if (offset + bytes > CONFIG_FLASH_SIZE_BYTES) + if (offset + bytes > CONFIG_FLASH_SIZE) return EC_ERROR_INVAL; cmd[0] = SPI_FLASH_READ; for (i = 0; i < bytes; i += read_size) { @@ -227,7 +227,7 @@ int spi_flash_erase(unsigned int offset, unsigned int bytes) int rv = EC_SUCCESS; /* Invalid input */ - if (offset + bytes > CONFIG_FLASH_SIZE_BYTES) + if (offset + bytes > CONFIG_FLASH_SIZE) return EC_ERROR_INVAL; /* Not aligned to sector (4kb) */ @@ -280,7 +280,7 @@ int spi_flash_write(unsigned int offset, unsigned int bytes, int rv, write_size; /* Invalid input */ - if (!data || offset + bytes > CONFIG_FLASH_SIZE_BYTES || + if (!data || offset + bytes > CONFIG_FLASH_SIZE || bytes > SPI_FLASH_MAX_WRITE_SIZE) return EC_ERROR_INVAL; @@ -435,8 +435,7 @@ int spi_flash_check_protect(unsigned int offset, unsigned int bytes) int rv = EC_SUCCESS; /* Invalid value */ - if (sr1 == 0xff || sr2 == 0xff || - offset + bytes > CONFIG_FLASH_SIZE_BYTES) + if (sr1 == 0xff || sr2 == 0xff || offset + bytes > CONFIG_FLASH_SIZE) return EC_ERROR_INVAL; /* Compute current protect range */ @@ -467,8 +466,7 @@ int spi_flash_set_protect(unsigned int offset, unsigned int bytes) uint8_t sr2 = spi_flash_get_status2(); /* Invalid values */ - if (sr1 == 0xff || sr2 == 0xff || - offset + bytes > CONFIG_FLASH_SIZE_BYTES) + if (sr1 == 0xff || sr2 == 0xff || offset + bytes > CONFIG_FLASH_SIZE) return EC_ERROR_INVAL; /* Compute desired protect range */ @@ -610,7 +608,7 @@ static int command_spi_flashread(int argc, char **argv) spi_enable(CONFIG_SPI_FLASH_PORT, 1); /* Can't read past size of memory */ - if (offset + bytes > CONFIG_FLASH_SIZE_BYTES) + if (offset + bytes > CONFIG_FLASH_SIZE) return EC_ERROR_INVAL; /* Wait for previous operation to complete */ diff --git a/common/spi_flash_reg.c b/common/spi_flash_reg.c index ee8d31fa06..3cee0f3bd4 100644 --- a/common/spi_flash_reg.c +++ b/common/spi_flash_reg.c @@ -163,7 +163,7 @@ int spi_flash_protect_to_reg(unsigned int start, unsigned int len, uint8_t *sr1, return EC_ERROR_INVAL; /* Invalid data */ - if ((start && !len) || start + len > CONFIG_FLASH_SIZE_BYTES) + if ((start && !len) || start + len > CONFIG_FLASH_SIZE) return EC_ERROR_INVAL; for (i = 0; i < ARRAY_SIZE(spi_flash_protect_ranges); ++i) { diff --git a/common/vboot_hash.c b/common/vboot_hash.c index 334b006281..e3bdf9e6fd 100644 --- a/common/vboot_hash.c +++ b/common/vboot_hash.c @@ -211,9 +211,8 @@ static int vboot_hash_start(uint32_t offset, uint32_t size, * Make sure request fits inside flash. That is, you can't use this * command to peek at other memory. */ - if (offset > CONFIG_FLASH_SIZE_BYTES || - size > CONFIG_FLASH_SIZE_BYTES || - offset + size > CONFIG_FLASH_SIZE_BYTES || nonce_size < 0) { + if (offset > CONFIG_FLASH_SIZE || size > CONFIG_FLASH_SIZE || + offset + size > CONFIG_FLASH_SIZE || nonce_size < 0) { return EC_ERROR_INVAL; } diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S index 9a23a419f6..fc24d181b5 100644 --- a/core/cortex-m/ec.lds.S +++ b/core/cortex-m/ec.lds.S @@ -503,7 +503,7 @@ SECTIONS /* * These linker labels are just for analysis and not used in the code. */ - __config_flash_size = CONFIG_FLASH_SIZE_BYTES; + __config_flash_size = CONFIG_FLASH_SIZE; __config_ro_size = CONFIG_RO_SIZE; __config_ec_protected_storage_size = CONFIG_EC_PROTECTED_STORAGE_SIZE; __config_rw_size = CONFIG_RW_SIZE; diff --git a/core/cortex-m0/ec.lds.S b/core/cortex-m0/ec.lds.S index 1241638361..6839b37778 100644 --- a/core/cortex-m0/ec.lds.S +++ b/core/cortex-m0/ec.lds.S @@ -315,7 +315,7 @@ SECTIONS /* * These linker labels are just for analysis and not used in the code. */ - __config_flash_size = CONFIG_FLASH_SIZE_BYTES; + __config_flash_size = CONFIG_FLASH_SIZE; __config_ro_size = CONFIG_RO_SIZE; __config_ec_protected_storage_size = CONFIG_EC_PROTECTED_STORAGE_SIZE; __config_rw_size = CONFIG_RW_SIZE; diff --git a/core/nds32/ec.lds.S b/core/nds32/ec.lds.S index 1d35041fea..4565600b05 100644 --- a/core/nds32/ec.lds.S +++ b/core/nds32/ec.lds.S @@ -285,7 +285,7 @@ SECTIONS /* * These linker labels are just for analysis and not used in the code. */ - __config_flash_size = CONFIG_FLASH_SIZE_BYTES; + __config_flash_size = CONFIG_FLASH_SIZE; __config_ro_size = CONFIG_RO_SIZE; __config_ec_protected_storage_size = CONFIG_EC_PROTECTED_STORAGE_SIZE; __config_rw_size = CONFIG_RW_SIZE; diff --git a/core/riscv-rv32i/ec.lds.S b/core/riscv-rv32i/ec.lds.S index e6d310cecb..c9de979d78 100644 --- a/core/riscv-rv32i/ec.lds.S +++ b/core/riscv-rv32i/ec.lds.S @@ -337,7 +337,7 @@ SECTIONS /* * These linker labels are just for analysis and not used in the code. */ - __config_flash_size = CONFIG_FLASH_SIZE_BYTES; + __config_flash_size = CONFIG_FLASH_SIZE; __config_ro_size = CONFIG_RO_SIZE; __config_ec_protected_storage_size = CONFIG_EC_PROTECTED_STORAGE_SIZE; __config_rw_size = CONFIG_RW_SIZE; diff --git a/docs/configuration/ec_chipset.md b/docs/configuration/ec_chipset.md index b006736712..5f04c4d81e 100644 --- a/docs/configuration/ec_chipset.md +++ b/docs/configuration/ec_chipset.md @@ -17,7 +17,7 @@ by the EC. ## Feature Parameters - - `CONFIG_FLASH_SIZE_BYTES <bytes>` - Set to the size of the internal flash of the + - `CONFIG_FLASH_SIZE <bytes>` - Set to the size of the internal flash of the EC. Must be defined to link the final image. - `CONFIG_SPI_FLASH_PORT <port>` - Only used if your board as an external flash. diff --git a/include/config.h b/include/config.h index bd82282993..159670cd2a 100644 --- a/include/config.h +++ b/include/config.h @@ -1820,7 +1820,7 @@ #undef CONFIG_FLASH_REGION_TYPE_COUNT /* Total size of writable flash */ -#undef CONFIG_FLASH_SIZE_BYTES +#undef CONFIG_FLASH_SIZE /* Minimum flash write size (in bytes) */ #undef CONFIG_FLASH_WRITE_SIZE diff --git a/include/config_std_internal_flash.h b/include/config_std_internal_flash.h index d272f5136c..4b722f86d9 100644 --- a/include/config_std_internal_flash.h +++ b/include/config_std_internal_flash.h @@ -37,7 +37,7 @@ * This is NOT a globally defined config, and is only used in this file * for convenience. */ -#define _IMAGE_SIZE ((CONFIG_FLASH_SIZE_BYTES - \ +#define _IMAGE_SIZE ((CONFIG_FLASH_SIZE - \ CONFIG_SHAREDLIB_SIZE) / 2) /* @@ -69,7 +69,7 @@ #define CONFIG_EC_PROTECTED_STORAGE_OFF 0 #define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF #define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE (CONFIG_FLASH_SIZE_BYTES - \ +#define CONFIG_EC_WRITABLE_STORAGE_SIZE (CONFIG_FLASH_SIZE - \ CONFIG_EC_WRITABLE_STORAGE_OFF) #define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF diff --git a/include/flash.h b/include/flash.h index 5fc6ae1055..7dfb309122 100644 --- a/include/flash.h +++ b/include/flash.h @@ -61,7 +61,7 @@ int flash_bank_erase_size(int bank); #else /* CONFIG_FLASH_MULTIPLE_REGION */ /* Number of physical flash banks */ #ifndef PHYSICAL_BANKS -#define PHYSICAL_BANKS (CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE) +#define PHYSICAL_BANKS (CONFIG_FLASH_SIZE / CONFIG_FLASH_BANK_SIZE) #endif /* WP region offset and size in units of flash banks */ diff --git a/include/rwsig.h b/include/rwsig.h index 425618490b..c43932b173 100644 --- a/include/rwsig.h +++ b/include/rwsig.h @@ -91,7 +91,7 @@ void rwsig_jump_now(void); * which might actually be in the PSTATE region. */ #define CONFIG_RO_PUBKEY_ADDR (CONFIG_PROGRAM_MEMORY_BASE \ - + (CONFIG_FLASH_SIZE_BYTES / 2) \ + + (CONFIG_FLASH_SIZE / 2) \ - CONFIG_RO_PUBKEY_SIZE) #endif #endif /* CONFIG_RO_PUBKEY_ADDR */ diff --git a/test/flash.c b/test/flash.c index 1b55d236d9..401e2bd6f4 100644 --- a/test/flash.c +++ b/test/flash.c @@ -353,7 +353,7 @@ static int test_flash_info(void) TEST_ASSERT(test_send_host_command(EC_CMD_FLASH_INFO, 1, NULL, 0, &resp, sizeof(resp)) == EC_RES_SUCCESS); - TEST_CHECK((resp.flash_size == CONFIG_FLASH_SIZE_BYTES) && + TEST_CHECK((resp.flash_size == CONFIG_FLASH_SIZE) && (resp.write_block_size == CONFIG_FLASH_WRITE_SIZE) && (resp.erase_block_size == CONFIG_FLASH_ERASE_SIZE) && (resp.protect_block_size == CONFIG_FLASH_BANK_SIZE)); diff --git a/test/test_config.h b/test/test_config.h index 9e4b2cc50a..51c2e5603d 100644 --- a/test/test_config.h +++ b/test/test_config.h @@ -565,7 +565,7 @@ int ncp15wb_calculate_temp(uint16_t adc); #define CONFIG_RW_B #define CONFIG_RW_B_MEM_OFF CONFIG_RO_MEM_OFF #undef CONFIG_RO_SIZE -#define CONFIG_RO_SIZE (CONFIG_FLASH_SIZE_BYTES / 4) +#define CONFIG_RO_SIZE (CONFIG_FLASH_SIZE / 4) #undef CONFIG_RW_SIZE #define CONFIG_RW_SIZE CONFIG_RO_SIZE #define CONFIG_RW_A_STORAGE_OFF CONFIG_RW_STORAGE_OFF |